The circular BIST design is a technique in which the existing circuit is modified, so that the processes of test generation and response compaction are carried out by the circuit being tested itself. Most response compaction techniques suffer from loss of information, known as aliasing. Aliasing is said to occur in a response compaction technique when the response generated by the circuit, under the presence of a fault, is different from its fault-free response, but this information is later lost during compaction, and the faulty compacted response at the end of the test session is identical to the fault-free compacted response.
A program to synthesize circular BIST hardware on general sequential circuits has been developed. A parallel fault simulator has been developed to detect aliasing errors in circular BIST design. Experimental results on aliasing probability in circular BIST design are reported for twenty-three sequential benchmark circuits. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/42137 |
| Date | 18 April 2009 |
| Creators | Kothari, Rajiv D. |
| Contributors | Electrical Engineering, Ha, Dong Sam, Armstrong, James R., Midkiff, Scott F. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Thesis, Text |
| Format | vii, 72 leaves, BTD, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | OCLC# 25119992, LD5655.V855_1991.K673.pdf |
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