Yes / In this letter a novel on-chip array antenna is investigated which is based on CMOS 20μm Silicon technology for operation over 0.6-0.65 THz. The proposed array structure is constructed on three layers composed of Silicon-Ground-Silicon layers. Two antennas are implemented on the top layer, where each antenna is constituted from three sub-antennas. The sub-antennas are constructed from interconnected dual-rings. Also, the sub-antennas are interconnected to each other. This approach enhances the aperture of the array. Surface waves and substrate losses in the structure are suppressed with metallic via-holes implemented between the radiation elements. To excite the structure, a novel feeding mechanism is used comprising open-circuited microstrip lines that couple electromagnetic energy from the bottom layer to the antennas on the top-layer through metasurface slot-lines in the middle ground-plane layer. The results show the proposed on-chip antenna array has an average radiation gain, efficiency, and isolation of 7.62 dBi, 32.67%, and -30 dB, respectively. / H2020-MSCA-ITN-2016 SECRET-722424 and the financial support from the UK Engineering and Physical Sciences Research Council (EPSRC) under grant EP/E0/22936/1
| Identifer | oai:union.ndltd.org:BRADFORD/oai:bradscholars.brad.ac.uk:10454/18118 |
| Date | 06 1900 |
| Creators | Alibakhshikenari, M., Virdee, B.S., See, C.H., Abd-Alhameed, Raed, Limiti, E. |
| Source Sets | Bradford Scholars |
| Language | English |
| Detected Language | English |
| Type | Conference paper, Accepted manuscript |
| Rights | © 2019 IEEE. Reproduced in accordance with the publisher's self-archiving policy. |
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