This thesis presents the CMOS integer-N frequency synthesizer for 5 GHz WCDMA applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection, and a pulse-swallow divider. In pulse-swallow divider, this thesis use true single phase clock DFF proposed by Yuan and Svensson to work on high frequency region and to save the circuit area and power. This thesis also proposes an auto-band selection circuit to control the output frequency more precise and easier, and it can also reduce the frequency drift effect caused by technology process or temperature variation.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0806107-105832 |
| Date | 06 August 2007 |
| Creators | Chen, Ming-Jing |
| Contributors | Shiann-Rong Kuang, Ko-Chi Kuo, Chia-Hsiung Kao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806107-105832 |
| Rights | not_available, Copyright information available at source archive |
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