A DRAM communicates with a processing unit via two interfaces: a data interface and a command interface. In today's DRAMs, also known as synchronous DRAMs (SDRAMs), both interfaces use a clock to communicate with the processing unit. The clock times the communication between the processing unit and the SDRAM on both the data interface and the command interface.
We propose a self-timed DRAM. The self-timed DRAM introduces more flexibility into the DRAM interface by eliminating the clock. The command interface and the data interface each communicate with the processing unit using a handshake protocol rather than a clock.
This thesis presents the data interface between the self-timed DRAM and the processing unit. The proposed data interface is self-timed. The self-timed data interface allows the DRAM to deliver data to or accept data from the processing unit as the processing unit demands rather than on a schedule set from the command interface.
The self-timed data interface is designed using GasP circuits and micropipeline circuits. The design is simulated in 180nm CMOs process technology using hspice. This thesis presents the effects of width mismatch on the self-timed data interface. The micropipeline is slightly faster than the GasP. Also, the thesis compares the self-timed DRAM data interface with synchronous DRAM for the data burst rate.
| Identifer | oai:union.ndltd.org:pdx.edu/oai:pdxscholar.library.pdx.edu:open_access_etds-2442 |
| Date | 24 September 2013 |
| Creators | Nerkar, Rajesh |
| Publisher | PDXScholar |
| Source Sets | Portland State University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Dissertations and Theses |
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