Indiana University-Purdue University Indianapolis (IUPUI) / The nanotechnology materials have been used for high sensitivity sensing devices due to their ability to alter their properties in response to the environmental parameters such as temperature, pressure, gas, electromagnetic, and chemicals. The features of employing nanoparticles on top of graphene thin film have driven the hypothesis of achieving high sensing nanotechnology devices.
This study demonstrates a novel approach for designing a low noise nanoparticle based gas sensing device with internet of things (IoT) capability. The system is capable of minimizing cross-talk between multiple channels of amplifiers arranged on one chip using guard rings. Graphene mono-layer is utilized as sensing material with the sensitivity catalyzed by addition of gold nano-particles on its surface. The signal from the sensing unit is received by an offset cancellation amplifying system using a system on chip (SoC) approach. IoT capability of the sensing device is developed using FRDM K64f micro-controller board which sends messages on IoT platform when a gas is sensed. The message is received by an application created and sent as an email or message to the user.
This study details the mathematical models of the graphene based gas sensing devices, and the interface circuitry that drives the differential potentials, resulting from the sensing unit. The study presents the simulation and practical model of the device, detailing the design approach of the processing unit within the SoC system and wireless implementation of it.
The sensing device was capable of sensing gas concentration from 5% to 100% using both the resistive and capacitive based models. The I-V characteristics of the FET sensing device was in agreeable with the other models. The SoC processing unit was designed using cadence tools, and simulation results showed very high CMRR that enable the amplifier to sense a very low signal received from the gas sensors. The cross talk noise was reduced by surrounding guard rings around the amplifier circuits. The layout was accomplished with 45nm technology and simulation showed an offset voltage of 17μV.
| Identifer | oai:union.ndltd.org:IUPUI/oai:scholarworks.iupui.edu:1805/11831 |
| Date | 12 1900 |
| Creators | Tanu, Tanu |
| Contributors | Rizkalla, Maher. E. |
| Source Sets | Indiana University-Purdue University Indianapolis |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
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