The LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be minimized to reduce the power delay product.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/276882 |
| Date | January 1988 |
| Creators | Song, Shiunn Luen Steven, 1960- |
| Contributors | Schrimpf, Ronald D. |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Thesis-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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