In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis. Detailed analysis and comparison of these architectures are addressed in order to choose the best architecture with minimized area cost and computation latency given the required bit accuracy. Based on the comparison, we have chosen the best architecture and implemented an IEEE single precision floating-point CORDIC processor. The mathematical analysis of the computation errors is done to minimize the bit width of the composing arithmetic components during implementation. The comparison results of different architectures also serve as a general guideline for the design of floating-point sine/cosine units. Finally, we study the application of the floating-point CORDIC to 3D graphics acceleration.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0902108-203251 |
| Date | 02 September 2008 |
| Creators | Lee, Hsin-mau |
| Contributors | Shiann-Rong Kuang, Shen-Fu Hsiao, Chuen-Yau Chen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251 |
| Rights | campus_withheld, Copyright information available at source archive |
Page generated in 0.0018 seconds