As wireless communication is ever-evolving, demanding higher data speeds, the requirementsincrease for the ADC, and the requirements for the comparator, which is one of the mainbuilding blocks, increase as well. The primary purpose of the comparator is to compare twovoltage levels and provide a logic output. One significant advantage of dynamic comparatorsis that they are more power-efficient than traditional comparators. There exist many differentarchitectures for dynamic comparators. In this thesis, the most promising designs areoptimized and evaluated over various parameters, such as speed, noise, offset, and hysteresis,while minimizing power consumption. The thesis includes a traditional StrongARM-latch,a double tail, and four triple tail comparators. The StrongARM-latch was the most powerefficientdesign while all the parameters were within the requirements, which was unexpected.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-187655 |
| Date | January 2022 |
| Creators | Lund, Pelle |
| Publisher | Linköpings universitet, Elektroniska Kretsar och System |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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