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Transmission Modeling and Channel Decoder Implementation Using FPGA for Homplug 1.0 Systems

In this thesis, we introduce a methodology to design and implement a Homeplug1.0 channel decoder that is completely conforming to Homeplug 1.0 specifications definedin HomePlug Power-line Alliance Standard (HPA) including Reed-solomon decoding,Viterbi decoding, punctured ,and de-interleaving technologies. Further, by using
MATLAB/Simullink software, Xilinx System Generator, Xilinx Alliance tools, XilinxISE and Modelsim SE software, we build up a transceiver platform to simulate and analyze the performance of the power-line channel decoder based on FPGA hardware
implementation. The hardware can be used directly in practical Homeplug 1.0 systems.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0901110-183033
Date01 September 2010
CreatorsLiu, Jia-Young
ContributorsPei-Yin Chen, Tsang-Yi Wang, Chao-Tang Yu
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-183033
Rightscampus_withheld, Copyright information available at source archive

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