Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal.

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

<p>The development in electronics increases the demand for good design methods and design tools in the field of electrical engeneering. To improve their design methods Ericsson Microwave Systems AB is interested in using computer tools to create a link between the specification and the implementation of a digital system in a FPGA. </p><p>Xilinx System Generator for DSP is a tool for implementing a model of a digital signalprocessing algorithm in a Xilinx FPGA. To evaluate Xilinx System Generator two testcases has been designed. </p><p>The testcases are selected to represent the FPGA designs made at Ericsson Microwave Systems. The testcases show that Xilinx System Generator can be used to effectivly implement a model made in Simulink in a FPGA from Xilinx. The result of the implementation is comparable to the implementation of VHDL code written by hand. </p><p>The use of tools for implementation of a model in hardware cause change in the design methods used at Ericsson Microwave Systems. The higher level of abstraction introduced by System Generator results in the design decisions made at system level having a higher impact on the final realization.</p>

The development in electronics increases the demand for good design methods and design tools in the field of electrical engeneering. To improve their design methods Ericsson Microwave Systems AB is interested in using computer tools to create a link between the specification and the implementation of a digital system in a FPGA. Xilinx System Generator for DSP is a tool for implementing a model of a digital signalprocessing algorithm in a Xilinx FPGA. To evaluate Xilinx System Generator two testcases has been designed. The testcases are selected to represent the FPGA designs made at Ericsson Microwave Systems. The testcases show that Xilinx System Generator can be used to effectivly implement a model made in Simulink in a FPGA from Xilinx. The result of the implementation is comparable to the implementation of VHDL code written by hand. The use of tools for implementation of a model in hardware cause change in the design methods used at Ericsson Microwave Systems. The higher level of abstraction introduced by System Generator results in the design decisions made at system level having a higher impact on the final realization.

In this thesis, we introduce a methodology to design and implement a Homeplug1.0 channel decoder that is completely conforming to Homeplug 1.0 specifications definedin HomePlug Power-line Alliance Standard (HPA) including Reed-solomon decoding,Viterbi decoding, punctured ,and de-interleaving technologies. Further, by using MATLAB/Simullink software, Xilinx System Generator, Xilinx Alliance tools, XilinxISE and Modelsim SE software, we build up a transceiver platform to simulate and analyze the performance of the power-line channel decoder based on FPGA hardware implementation. The hardware can be used directly in practical Homeplug 1.0 systems.

The rapid growth of communication technology with the success of internet, has brought huge profits and great convenience to our daily life. Computer networks can be built using either wired or wireless technologies. It will be an important issue that how to select a medium for the transmission. Wired Ethernet has been the traditional choice in most of the networks. However, it has to deploy the Ethernet wires. For the wired internet networks, the power line communication (PLC) technology will be an alternative choice. In this wire-line communication system, the power line network is used as the transmission medium. Therefore, computer networks can work on the existing power line system. No extra new transmission infrastructure is needed. So far, several PLC standards are available, shch as X-10, CEBus(Consumer Electronic Bus), Echonet and Homeplug. This thesis studies the Homeplug AV specification developed by the Homeplug powerline Alliance. By employing MATLAB/Simulink, we build up a PLC baseband transmission model and simulation platform. We carry out the Homeplug AV baseband transmission performance in system level on this platform. The Homeplug AV adopts 3072-point FFT which is not the power of two. It will be a challenge to design the 3072-point FFT processor. Here, we use Xilinx System Generator to design and implement the 3072-point FFT processor. The function verification of the implemented 3072-point FFT processor for Homeplug AV system is carried out by simulation.

Orientador: Luis Geraldo Pedroso Meloni / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T05:58:36Z (GMT). No. of bitstreams: 1 LemesFilho_JoseMatias.pdf: 2987431 bytes, checksum: 93fc757a06215b93a08427d2f33f88a2 (MD5) Previous issue date: 2009 / Resumo: Este trabalho descreve o estudo, a pesquisa e compilação de técnicas de otimização de códigos em FPGA (Field Programmable Gate Arrays) utilizando uma ferramenta de prototipagem rápida. Para isso, foram implementados alguns algoritmos para auxiliar na apresentação e avaliação de quatro técnicas de otimização: uso de recursos alternativos, multiplexação no tempo, algoritmos alternativos e mudança da freqüência sistêmica. As principais contribuições do presente trabalho foram: compilar em um único documento diversas técnicas para geração eficiente de códigos de processamento digital de sinais; o estudo das etapas de fluxo de projeto baseado em ferramentas de prototipagem rápida; implementações de diversos algoritmos para demonstrar as técnicas de otimização, visando-se o estudo da minimização da área de ocupação em FPGA. Com o uso das técnicas pode-se alcançar uma redução de área da FPGA de até 90%, conforme a complexidade do sistema alvo. / Abstract: This work describes the study, research and compilation of programming optimization techniques for FPGA (Field Programmable Gate Arrays) using a tool technology for rapid prototyping. For this purpose, some algorithms have been implemented to help the presentation and evaluation of four optimization techniques: alternative resources usage, time multiplexing, alternative algorithms and systemic frequency change. The main contributions of this work are: compilation in one document several efficient techniques for generation code in digital signal processing; study of the phases of design flow were based on rapid prototyping tools; implementations of several algorithms to demonstrate the optimization techniques, looking for the minimization of the FPGA occupation area. With the use of these techniques, it is possible to reach a FPGA area reduction of up to 90%, depending of the complexity of the target system. / Universidade Estadual de Campi / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

This Master’s Thesis is an evaluation of the software Xilinx System Generator (XSG) and blockset for Matlab. XSG is a module to simulink developed by Xilinx in order to generate VHDL code directly from functions implemented in Matlab. The evaluation was made at Saab Avionics AB in Järfälla, north of Stockholm. In order to investigate the performance of this new module XSG to simulink, a model of a frequency estimator often used in digital radar receivers were implemented in Matlab using XSG. Engineers working at SAAB Avionics implemented the same application directly in VHDL, without using Matlab and the XSG. After generating code the results were synthesised, analysed and compared. The frequency estimator basically contains an FFT, a windowing function and a sorting algorithm used to enable analyse of two real signals simultaneously. There were however problems during generation of the VHDL code and the model had to be broken into smaller parts containing only a 16-point FFT. The results of comparison in this report are based on models containing only this 16-point FFT and they show a small advantage for the System Generator according to the resource usage report generated during synthesis. Designing models for generation using Xilinx Blockset can create a lot of wiring between components. The reason for this is that the System Generator and Xilinx Blockset today is a new tool, not completely developed. There are many components found in simulink, Matlab that could not be found in Xilinx Blockset, this is however being improved. Another problem is long time for simulation and errors during generation. My opinion is that when used for smaller systems and with further development the System Generator can be a useful facility in designing digital electronics.

<p>This Master’s Thesis is an evaluation of the software Xilinx System Generator (XSG) and blockset for Matlab. XSG is a module to simulink developed by Xilinx in order to generate VHDL code directly from functions implemented in Matlab. The evaluation was made at Saab Avionics AB in Järfälla, north of Stockholm. </p><p>In order to investigate the performance of this new module XSG to simulink, a model of a frequency estimator often used in digital radar receivers were implemented in Matlab using XSG. Engineers working at SAAB Avionics implemented the same application directly in VHDL, without using Matlab and the XSG. After generating code the results were synthesised, analysed and compared. </p><p>The frequency estimator basically contains an FFT, a windowing function and a sorting algorithm used to enable analyse of two real signals simultaneously. There were however problems during generation of the VHDL code and the model had to be broken into smaller parts containing only a 16-point FFT. The results of comparison in this report are based on models containing only this 16-point FFT and they show a small advantage for the System Generator according to the resource usage report generated during synthesis. </p><p>Designing models for generation using Xilinx Blockset can create a lot of wiring between components. The reason for this is that the System Generator and Xilinx Blockset today is a new tool, not completely developed. There are many components found in simulink, Matlab that could not be found in Xilinx Blockset, this is however being improved. Another problem is long time for simulation and errors during generation. </p><p>My opinion is that when used for smaller systems and with further development the System Generator can be a useful facility in designing digital electronics.</p>