In some applications polynomials should be evaluated, e.g., polynomial approximation of elementary function and Farrow filter for arbitrary re-sampling. For polynomial evaluation Horner’s scheme uses the minimum amount of hardware resources, but it is sequential. Many algorithms were developed to introduce parallelism in polynomial evaluation. This parallelism is achieved at the cost of hardware, but ensures evaluation in less time. This work examines the trade-off between hardware cost and the critical path for different level of parallelism for polynomial evaluation. The trade-offs in generating powers in polynomial evaluation using different building blocks(squarers and multipliers) are also discussed. Wordlength requirements of the polynomial evaluation and the effect of power generating schemes on the timing of operations is also discussed. The area requirements are calculated by using Design Analyzer from Synopsys (tool for logic synthesis) and the GLPK (GNU Linear Programming Kit) is used to calculate the bit requirements.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-60054 |
| Date | January 2010 |
| Creators | Nawaz Khan, Shahid |
| Publisher | Linköpings universitet, Elektroniksystem |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/masterThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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