<p>In some applications polynomials should be evaluated, e.g., polynomial approximation of elementary function and Farrow filter for arbitrary re-sampling. For polynomial evaluation Horner’s scheme uses the minimum amount of hardware resources, but it is sequential. Many algorithms were developed to introduce parallelism in polynomial evaluation. This parallelism is achieved at the cost of hardware, but ensures evaluation in less time.</p><p>This work examines the trade-off between hardware cost and the critical path for different level of parallelism for polynomial evaluation. The trade-offs in generating powers in polynomial evaluation using different building blocks(squarers and multipliers) are also discussed. Wordlength requirements of the polynomial evaluation and the effect of power generating schemes on the timing of operations is also discussed. The area requirements are calculated by using Design Analyzer from Synopsys (tool for logic synthesis) and the GLPK (GNU Linear Programming Kit) is used to calculate the bit requirements.</p>

In some applications polynomials should be evaluated, e.g., polynomial approximation of elementary function and Farrow filter for arbitrary re-sampling. For polynomial evaluation Horner’s scheme uses the minimum amount of hardware resources, but it is sequential. Many algorithms were developed to introduce parallelism in polynomial evaluation. This parallelism is achieved at the cost of hardware, but ensures evaluation in less time. This work examines the trade-off between hardware cost and the critical path for different level of parallelism for polynomial evaluation. The trade-offs in generating powers in polynomial evaluation using different building blocks(squarers and multipliers) are also discussed. Wordlength requirements of the polynomial evaluation and the effect of power generating schemes on the timing of operations is also discussed. The area requirements are calculated by using Design Analyzer from Synopsys (tool for logic synthesis) and the GLPK (GNU Linear Programming Kit) is used to calculate the bit requirements.

Un circuit arithmétique dont les entrées sont des entiers ou une variable x et dont les portes calculent la somme ou le produit représente un polynôme univarié. On assimile la complexité de représentation d'un polynôme par un circuit arithmétique au nombre de portes multiplicatives minimal requis pour cette modélisation. Et l'on cherche à obtenir une borne inférieure à cette complexité, et cela en fonction du degré d du polynôme. A une chaîne additive pour d, correspond un circuit arithmétique pour le monôme de degré d. La conjecture de Strassen prétend que le nombre minimal de portes multiplicatives requis pour représenter un polynôme de degré d est au moins la longueur minimale d'une chaîne additive pour d. La conjecture de Strassen généralisée correspondrait à la même proposition lorsque les portes du circuit arithmétique ont degré entrant g au lieu de 2. Le mémoire consiste d'une part en une généralisation du concept de chaînes additives, et une étude approfondie de leur construction. On s'y intéresse d'autre part aux polynômes qui peuvent être représentés avec très peu de portes multiplicatives (les d-gems). On combine enfin les deux études en lien avec la conjecture de Strassen. On obtient en particulier de nouveaux cas de circuits vérifiant la conjecture. / An arithmetic circuit with inputs among x and the integers which has product gates and addition gates represents a univariate polynomial. We define the complexity of the representation of a polynomial by an arithmetic circuit as the minimal number of product gates required for this modelization. And we seek a lower bound to this complexity, with respect to the degree d of the polynomial. An addition chain for d corresponds to an arithmetic circuit computing the monomial of degree d. Strassen's conjecture states that the minimal number of product gates required to represent a polynomial of degree d is at least the minimal length of an addition chain for d. The generalized Strassen conjecture corresponds to the same statement where the indegree of the gates of the arithmetic circuit is g instead of 2. The thesis consists, on the one hand, of the generalization of the concept of addition chains, and a study of the subject. On the other hand, it is concerned with polynomials which can be represented with very few product gates (d-gems). Both studies related to Strassen's conjecture are combined. In particular, we get new classes of circuits verifying the conjecture.

Un circuit arithmétique dont les entrées sont des entiers ou une variable x et dont les portes calculent la somme ou le produit représente un polynôme univarié. On assimile la complexité de représentation d'un polynôme par un circuit arithmétique au nombre de portes multiplicatives minimal requis pour cette modélisation. Et l'on cherche à obtenir une borne inférieure à cette complexité, et cela en fonction du degré d du polynôme. A une chaîne additive pour d, correspond un circuit arithmétique pour le monôme de degré d. La conjecture de Strassen prétend que le nombre minimal de portes multiplicatives requis pour représenter un polynôme de degré d est au moins la longueur minimale d'une chaîne additive pour d. La conjecture de Strassen généralisée correspondrait à la même proposition lorsque les portes du circuit arithmétique ont degré entrant g au lieu de 2. Le mémoire consiste d'une part en une généralisation du concept de chaînes additives, et une étude approfondie de leur construction. On s'y intéresse d'autre part aux polynômes qui peuvent être représentés avec très peu de portes multiplicatives (les d-gems). On combine enfin les deux études en lien avec la conjecture de Strassen. On obtient en particulier de nouveaux cas de circuits vérifiant la conjecture. / An arithmetic circuit with inputs among x and the integers which has product gates and addition gates represents a univariate polynomial. We define the complexity of the representation of a polynomial by an arithmetic circuit as the minimal number of product gates required for this modelization. And we seek a lower bound to this complexity, with respect to the degree d of the polynomial. An addition chain for d corresponds to an arithmetic circuit computing the monomial of degree d. Strassen's conjecture states that the minimal number of product gates required to represent a polynomial of degree d is at least the minimal length of an addition chain for d. The generalized Strassen conjecture corresponds to the same statement where the indegree of the gates of the arithmetic circuit is g instead of 2. The thesis consists, on the one hand, of the generalization of the concept of addition chains, and a study of the subject. On the other hand, it is concerned with polynomials which can be represented with very few product gates (d-gems). Both studies related to Strassen's conjecture are combined. In particular, we get new classes of circuits verifying the conjecture.

The aim of this dissertation is to improve computational efficiency of modular exponentiation-based public-key cryptosystems. The operational speed of these public-key cryptosystems is largely determined by the modular exponentiation operation of the form A = ge mod m where g is the base, e is the exponent and m is the modulus. The required modular exponentiation is computed by a series of modular multiplications. Optimized algorithms are required for various platforms, especially for lower-end platforms. These require the algorithms to be efficient and consume as little resources as possible. In these dissertation algorithms for integer multiplication, modular reduction and modular exponentiation, was developed and implemented in software, as required for public-key cryptography. A detailed analysis of these algorithms is given, as well as exact measurement of the computational speed achieved by each algorithm. This research shows that a total speed improvement of 13% can be achieved on existing modular exponentiation based public-key cryptosystems, in particular for the RSA cryptosystem. Three novel approaches are also presented for improving the decryption speed efficiency of the RSA algorithm. These methods focus on the selection of the decryption exponent by careful consideration of the difference between the two primes p and q. The resulting reduction of the decryption exponent improves the decryption speed by approximately 45%. / Dissertation (MEng (Electronics))--University of Pretoria, 2006. / Electrical, Electronic and Computer Engineering / unrestricted