Performance modelling and high performance buffer design for the system with network on chip

Description

Thesis (Ph. D.)--Washington State University, December 2007. / Includes bibliographical references (p. 107-112).

Links & Downloads

1. http://www.dissertations.wsu.edu/Dissertations/Fall2007/j_liu_111907.pdf

Tags

Systems on a chip. Integrated circuits

Additional Fields

Identifer	oai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/183334631
Date	January 2007
Creators	Liu, Jin,
Source Sets	OCLC
Language	English
Detected Language	English
Source	Online access for everyone