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Wireless Interconnect for Board and Chip Level

Electronic systems of the future require a very high bandwidth communications infrastructure within the system. This way the massive amount of compute power which will be available can be inter-connected to realize future powerful advanced electronic systems. Today, electronic inter-connects between 3D chip-stacks, as well as intra-connects within 3D chip-stacks are approaching data rates of 100 Gbit/s soon. Hence, the question to be answered is how to efficiently design the communications infrastructure which will be within electronic systems. Within this paper approaches and results for building this infrastructure for future electronics are addressed.

Identiferoai:union.ndltd.org:DRESDEN/oai:qucosa.de:bsz:14-qucosa-118302
Date11 July 2013
CreatorsFettweis, Gerhard P., ul Hassan, Najeeb, Landau, Lukas, Fischer, Erik
ContributorsTechnische Universität Dresden, Sonderforschungsbereich 912
PublisherSaechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden
Source SetsHochschulschriftenserver (HSSS) der SLUB Dresden
LanguageEnglish
Detected LanguageEnglish
Typedoc-type:conferenceObject
Formatapplication/pdf
SourceProceedings of the Design Automation and Test in Europe (DATE), 2013, S. 958 - 963, ISSN: 1530-1591

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