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Leakage power modeling and reduction techniques for nanometer scale VLSI circuits /

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/57859352
Date January 2004
CreatorsAu, Yi-ching.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceView abstract or full-text.

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