A 5 GHZ low power, low jitter and fast settling phase locked loop architecture for wireline and wireless transceiver

Description

Thesis (Ph. D.)--Washington State University, August 2008. / Includes bibliographical references (p. 84-85).

Links & Downloads

1. http://www.dissertations.wsu.edu/Dissertations/Summer2008/P_Upadhyaya_072308.pdf

Tags

Radio Phase-locked loops.

Additional Fields

Identifer	oai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/252264962
Date	January 2008
Creators	Upadhyaya, Parag.
Source Sets	OCLC
Language	English
Detected Language	English
Source	Online access for everyone