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A low power 10 GHz phase locked loop for radar applications implemented in 0.13 um SiGe technologySouder, William, Dai, Foster, January 2009 (has links)
Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographical references (p. 83-85).
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Oscillator Architectures and Enhanced Frequency SynthesizerPark, Sang Wook 14 March 2013 (has links)
A voltage controlled oscillator (VCO), that generates a periodic signal whose
frequency is tuned by a voltage, is a key building block in any integrated circuit systems.
A sine wave oscillator can be used for a built-in self testing where high linearity is
required. A bandpass filter (BPF) based oscillator is a preferred solution, and high
quality factor (Q-factor) is needed to improve the linearity. However, a stringent
linearity specification may require very high Q-factor, not practical to implement. To
address this problem, a frequency harmonic shaping technique is proposed. It utilizes a
finite impulse response filter improving the linearity by rejecting certain harmonics. A
prototype SC BPF oscillator with an oscillating frequency of 10 MHz is designed and
measurement results show that linearity is improved by 20 dB over a conventional
oscillator.
In radio frequency area, preferred oscillator structures are an LC oscillator and a
ring oscillator. An LC oscillator exhibits good phase noise but an expensive cost of an
inductor is disadvantageous. A ring oscillator can be built in standard CMOS process,
but suffers due to a poor phase noise and is sensitive to supply noise. A RC BPF
oscillator is proposed to compromise the above difficulties. A RC BPF oscillator at 2.5
GHz is designed and measured performance is better than ring oscillators when
compared using a figure of merit. In particular, the frequency tuning range of the
proposed oscillator is superior to the ring oscillator.
VCO is normally incorporated with a frequency synthesizer (FS) for an accurate
frequency control. In an integer-N FS, reference spur is one of the design concerns in
communication systems since it degrades a signal to noise ratio. Reference spurs can be
rejected more by either the lower loop bandwidth or the higher loop filter. But the
former increases a settling time and the latter decreases phase margin. An adaptive
lowpass filtering technique is proposed. The loop filter order is adaptively increased
after the loop is locked. A 5.8 GHz integer-N FS is designed and measurement results
show that reference spur rejection is improved by 20 dB over a conventional FS without
degrading the settling time. A new pulse interleaving technique is proposed and several
design modifications are suggested as a future work.
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STRONG SIGNAL LASER THEORYHambenne, Jarel Bennett, 1942- January 1975 (has links)
No description available.
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A methodology for modeling noise and spurious responses in phase-locked loopsThain, Walter E., 12 1900 (has links)
No description available.
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A 5 GHZ low power, low jitter and fast settling phase locked loop architecture for wireline and wireless transceiverUpadhyaya, Parag. January 2008 (has links) (PDF)
Thesis (Ph. D.)--Washington State University, August 2008. / Includes bibliographical references (p. 84-85).
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Phase-Locked Loop Simulation in Transient Stabilities StudiesMartin, Louis V. January 1989 (has links)
Note:
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A low Jitter Wide-range Delay-Locked Loop with the Rail to Rail Differential Multi Control Delay Line ImplementationTsai, Yi-Sing 12 August 2010 (has links)
A Rail to Rail Differential Control Delay Line using multi-band technology can provide wider range on a delay-locked loop (DLL) is proposed in this thesis. Delay-Locked Loops (DLLs) have been widely used for clock deskew instead of Phase-Locked Loop (PLLs) because of easy design and inherent stable.
The main object of this thesis is the description and discussion in Delay-Locked Loop and Rail to Rail Differential Control Delay Line; uses TSMC 0.18£gm 1P6M CMOS process to design a 70 MHz¡ã750 MHz DLL and the supply voltage is 1.8V.
This thesis is characterized by utilizing rail to rail input to reduce noise interference and enhance the signal integrity¡]low distortion, low noise, low power and high gain¡^.By the phase selection circuit is used to extend operation frequency. The operate frequency range of DLL is 70MHz to 750MHz, the power consumption of the Entire system is less than 32mW. The phase error is 10 ps at 70MHz and <10 ps at 750MHz in lock. The proposed DLL can provide wider range and lower jitter in this thesis.
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Low Power, Fast Locking, and Wide-Range Delay-locked Loop for Clock Generator.Hsu, Yi-hsi 16 July 2008 (has links)
This thesis presents a delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-controlled delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-controlled delay line. By using multi-band technology the proposed DLL can provide wider range and lower jitter compared to those of other methods. Frequency can be ranged from 250MHz to 900MHz is using TSMC 0.18um process with 1.8V supply voltage. The other implement is using UMC 90nm 1P9M CMOS process with 1V supply voltage. The frequency can be ranged from 33MHz to 300MHz.
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High Performance Sub-Sampling Phase Detector based Ring-Oscillator Phase-Locked LoopsNagam, Shravan Siddartha January 2020 (has links)
Phase locked loops (PLLs) used to generate high precision clocks are integral components in the majority of modern day electronic systems such as Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC), transceivers, processors, etc. The accuracy of this clocks that effects the overall performance of the system is measured in terms of its jitter, phase noise, spurious tones, etc. For example, the jitter in an ADC sampling clock can result in uncertainty of the sampling instant and can result in degradation of the effective number of bits (ENOB) of the ADC, phase noise on the other hand can result in reciprocal mixing in receivers and leakage into adjacent channels in transmitters. Therefore it is very desirable to design PLLs that generate clean clocks with minimal area and power consumption.
This thesis discusses two PLL prototypes in 65nm CMOS technology. The first prototype demonstrates a sub-sampling phase detector (SSPD) based feed-forward noise cancellation (FFNC) scheme in a Type-II ring oscillator (RO) PLL. The FFNC technique uses the already available noise information at the SSPD output and cancels it from the PLL output. The proposed FFNC achieves a 1.4x reduction in jitter, 19.5dB power supply induced noise suppression at the PLL output while consuming a small area of 0.022mm2.
The second prototype demonstrates a Type-I SSPD based RO PLL. The SSPD sample-and-hold action generates a steady-state voltage to tune the VCO directly. This eliminates the issue of high reference spurs generally associated with a Type-I PLL. Also the Type-I PLL occupies a very low area of 0.008mm2 as it avoids the usage of bulky integrating capacitor generally used in a Type-II PLL. The PLL with 2.4GHz output achieves a phase noise of -122.6dBc/Hz at a 1MHz offset and the power consumption is 6.1mW. It achieves reference spurs of -64.2dBc, RMSjitter of 422fs and FoMjitter of -239.7dB.
In addition to the two prototypes, a theoretical discussion on an auxiliary FFNC (AFFNC) cancellation scheme that can work with a generic Type-II RO PLL is also included. The AFFNC technique uses a stand alone SSPD to extract and cancel noise from the VCO output. The SSPD is embedded into an alignment loop for proper noise extraction and cancellation. Along with AFFNC, which uses one reference edge for noise extraction, a Double Sampled AFFNC (DS-AFFNC) which utilizes both the rising and falling edge of the reference for noise extraction is also included. By using both the reference edges, higher cancellation BW is achieved.
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Tunable erbium doped fibre lasersGloag, Andrew John January 1996 (has links)
No description available.
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