This master‘s final paper describes JTAG (boundary scan) interface in which discuss IEEE standart 1149.1 circuit model and the main TAP (Test Access Port) controllers instructions. Accomplished programmable integral logical ICs overview: development, leading manufacturer (ALTERA, XILINX, ACTEL) production and programmable equipment evaluation. Represented recomendation, how we can pick suitable programmable logical device. The paper presents detailed describe searching ICs family XC9500 characteristic, features and merits. In general terms presented programmable logic language VHDL value. It also produces some detailed compose describes of the project, using methods of circuit drawing and VHDL language. Master‘s hypothesis that if we will use JTAG interface processed logical programmable instrumentation in our projects we can save up time, area and improve their quality is confirmed. This is prospective technology which also soon will be in use in Lithuania.
| Identifer | oai:union.ndltd.org:LABT_ETD/oai:elaba.lt:LT-eLABa-0001:E.02~2005~D_20050615_150741-49753 |
| Date | 15 June 2005 |
| Creators | Vismantas, Tomas |
| Contributors | Daunys, Gintautas, Laurutis, Remigijus, Laurutis, Vincas, Lauruška, Vidas, Buinevičius, Vytautas Algimantas, Siauliai University |
| Publisher | Lithuanian Academic Libraries Network (LABT), Siauliai University |
| Source Sets | Lithuanian ETD submission system |
| Language | Lithuanian |
| Detected Language | English |
| Type | Master thesis |
| Format | application/pdf |
| Source | http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050615_150741-49753 |
| Rights | Unrestricted |
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