Memory unit has become a major core component in most SoC designs, and thus reusable memory IP is crucial in speeding up the design process. In this thesis, we develop a low-power SRAM generator to reduce the design efforts by producing all the files required in traditional cell-based design flow. Several methods are used to reduce power consumption in the memory circuits, including hierarchical word-line architecture and block amplifiers. The SRAM generator can be extended to generate cache memory with mixed hard IP and soft IP where cache memory cells are hard IP while the cache controller is soft IP. Based on the SRAM generator, we can also generate some popular memory units such as register files, FIFO, LIFO, and delay elements used in many applications.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0903108-125651 |
| Date | 03 September 2008 |
| Creators | Tsung, Chih-qu |
| Contributors | Sian-Rong Kuang, Shen-Fu Hsiao, Chuen-Yau Chen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0903108-125651 |
| Rights | not_available, Copyright information available at source archive |
Page generated in 0.0022 seconds