The advancement in the CATV industry has been remarkable. In the beginning, CATV provided a few television channels. Now it provides a variety of advanced services such as video on demand (VOD), Internet access, Pay-Per-View on demand
and interactive TV. These advances have increased the popularity of CATV manyfold. Current improvements focus on interactive services with high quality. These
interactive services require more upstream (transmission from customer premises to cable operator premises) channel bandwidth.
The flow of data through the CATV network in both the upstream and downstream directions is governed by a standard referred to as the Data Over Cable Service Interface Specification (DOCSIS) standard. The latest version is DOCSIS 3.1,
which was released in January 2014. The previous version, DOCSIS 3.0, was released in 2006.
One component of the upstream communication link is the QAM demodulator. An important component in the QAM demodulator is the equalizer, whose purpose
is to remove distortion caused by the imperfect upstream channel as well as the residual timing offset and frequency offset. Most of the timing and frequency offset are corrected by timing and frequency recovery circuits; what remains is referred to
as offset.
A DOCSIS receiver, and hence the equalizer within, can be implemented with ASIC or FPGA technology. Implementing an equalizer in an ASIC has a large nonrecurring
engineering cost, but relatively small per chip production cost. Implementing equalizer in an FPGA has very low non-recurring cost, but a relatively high per chip cost. If the choice technology was based on cost, one would think it would depends only on the volume, but in practice that is not the case. The dominant factor when it comes to profit, is the time-to-market, which makes FPGA technology the
only choice.
The goal of this thesis is to design a cost optimized equalizer for DOCSIS upstream demodulator and implement in an FPGA. With this in mind, an important objective is to establish a relationship between the equalizer’s critical parameters
and its performance. The parameter-performance relationship that has been established in this study revealed that equalizer step size and length parameters should be
1/64 and approximately 20 to yield a near optimum equalizer when considering the MER-convergence time trade-off.
In the pursuit of the objective another relationship was established that is useful in determining the accuracy of the timing recovery circuit. That relationship establishes the sensitivity both of the MER and convergence time to timing offset.
The equalizer algorithm was implemented in a cost effective manner using DSP Builder. The effort to minimize cost was focused on minimizing the number of multipliers.
It is shown that the equalizer can be constructed with 8 multipliers when the proposed time sharing algorithm is implemented.
| Identifer | oai:union.ndltd.org:USASK/oai:ecommons.usask.ca:10388/ETD-2014-03-1454 |
| Date | 2014 March 1900 |
| Contributors | Salt, Joseph E., Saadat Mehr, Aryan |
| Source Sets | University of Saskatchewan Library |
| Language | English |
| Detected Language | English |
| Type | text, thesis |
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