The use of Community Antenna Television Network (CATV) cable systems are a very common way that subscribers use to access the internet and download data. The transmitters that send the signals to subscribers must conform to a very stringent specification known as DOCSIS. Using traditional high frequency design techniques to meet this specification often lead to a lengthy and difficult production process where several calibrations have to be made. In order to send a digitally modulated signal that conforms to the DOCSIS specification some sort of conversion between the discrete digital domain and the analog domain must occur. To accomplish this a Digital to Analog converter is used. In recent years, the clocking or sampling frequency that can be used for Digital to Analog converters (DACs) has been rapidly increasing. The clocking frequency is directly proportional to the bandwidth that can be transmitted. DAC's that have exceptionally high clocking frequencies can be referred to as Radio Frequency DAC's. The clocking frequency of these devices has now progressed to the point where direct digital synthesis can be used for a DOCSIS transmitter without any analog frequency conversion stages. Since Radio Frequency DAC's are real devices the output is not a perfect representation of the discrete signal that is sent to it. Unwanted distortion is added that can be measured at the analog output. Removal of this distortion or at least significantly reducing it could be the difference meeting or or not meeting the DOCSIS specification. This thesis will explore the usage of these devices in this application. The basic structure of DAC's as well as the distortion signals themselves will be investigated in order to develop a method where the distortion can be removed. Ideally this can be done in a way that is suitable to be integrated into a transmitter architecture and meet the specification. The frequency response of the major distortion products across the DOCSIS band is measured. Once this is done a way to match these frequency responses is needed so a cancellation signal can be created that removes the distortion. A method is developed that uses an iterative algorithm to find filter coefficients whose frequency response matches that of the distortion signals as closely as possible. Since these cancellation signals are added to the discrete signal to be transmitted before the interface with the Radio Frequency DAC the process is known as pre-distortion. The generated coefficients are used in digital filters as part of a pre-distortion design. Tests are performed with discrete signals that are close approximates to a DOCSIS signal that would be sent to a subscriber. Measured results show a decrease in the power of targeted distortion signals. The reduction of the distortion level is enough that the DOCSIS specification is met for all test signals.

The advancement in the CATV industry has been remarkable. In the beginning, CATV provided a few television channels. Now it provides a variety of advanced services such as video on demand (VOD), Internet access, Pay-Per-View on demand and interactive TV. These advances have increased the popularity of CATV manyfold. Current improvements focus on interactive services with high quality. These interactive services require more upstream (transmission from customer premises to cable operator premises) channel bandwidth. The flow of data through the CATV network in both the upstream and downstream directions is governed by a standard referred to as the Data Over Cable Service Interface Specification (DOCSIS) standard. The latest version is DOCSIS 3.1, which was released in January 2014. The previous version, DOCSIS 3.0, was released in 2006. One component of the upstream communication link is the QAM demodulator. An important component in the QAM demodulator is the equalizer, whose purpose is to remove distortion caused by the imperfect upstream channel as well as the residual timing offset and frequency offset. Most of the timing and frequency offset are corrected by timing and frequency recovery circuits; what remains is referred to as offset. A DOCSIS receiver, and hence the equalizer within, can be implemented with ASIC or FPGA technology. Implementing an equalizer in an ASIC has a large nonrecurring engineering cost, but relatively small per chip production cost. Implementing equalizer in an FPGA has very low non-recurring cost, but a relatively high per chip cost. If the choice technology was based on cost, one would think it would depends only on the volume, but in practice that is not the case. The dominant factor when it comes to profit, is the time-to-market, which makes FPGA technology the only choice. The goal of this thesis is to design a cost optimized equalizer for DOCSIS upstream demodulator and implement in an FPGA. With this in mind, an important objective is to establish a relationship between the equalizer’s critical parameters and its performance. The parameter-performance relationship that has been established in this study revealed that equalizer step size and length parameters should be 1/64 and approximately 20 to yield a near optimum equalizer when considering the MER-convergence time trade-off. In the pursuit of the objective another relationship was established that is useful in determining the accuracy of the timing recovery circuit. That relationship establishes the sensitivity both of the MER and convergence time to timing offset. The equalizer algorithm was implemented in a cost effective manner using DSP Builder. The effort to minimize cost was focused on minimizing the number of multipliers. It is shown that the equalizer can be constructed with 8 multipliers when the proposed time sharing algorithm is implemented.

The cable television (CATV) industry has grown significantly since its inception in the late 1940’s. Originally, a CATV network was comprised of several homes that were connected to community antennae via a network of coaxial cables. The only signal processing done was by an analogue amplifier, and transmission only occurred in one direction (i.e. from the antennae/head-end to the subscribers). However, as CATV grew in popularity, demand for services such as pay-per-view television increased, which lead to supporting transmission in the upstream direction (i.e. from subscriber to the head-end). This greatly increased the signal processing to include frequency diplexers. CATV service providers began to expand the bandwidth of their networks in the late 90’s by switching from analogue to digital technology. In an effort to regulate the manufacturing of new digital equipment and ensure interoperability of products from different manufacturers, several cable service providers formed a non-for-profit consortium to develop a data-over-cable service interface specification (DOCSIS). The consortium, which is named CableLabs, released the first DOCSIS standard in 1997. The DOCSIS standard has been upgraded over the years to keep up with increased consumer demand for large bandwidths and faster transmission speeds, particularly in the upstream direction. The latest version of the DOCSIS standard, DOCSIS 3.1, utilizes orthogonal frequency-division multiple access (OFDMA) technology to provide upstream transmission speeds of up to 1 Gbps. As cable service providers begin the process of upgrading their upstream receivers to comply with the new DOCSIS 3.1 standard, they require a means of testing the various functions that an upstream receiver may employ. It is convenient for service providers to employ cable modem (CM) plus channel emulator to perform these tests in-house during the product development stage. Constructing the emulator in digital technology is an attractive option for testing. This thesis approaches digital emulation by developing a digital model of the CMs and upstream channel in a DOCSIS 3.1 network. The first step in building the emulator is to simulate its operations in MATLAB, specifically upstream transmission over the network. The MATLAB model is capable of simulating transmission from multiple CMs, each of which transmits using a specific “transmission mode.” The three transmission modes described in the DOCSIS 3.1 standard are included in the model. These modes are “traffic mode,” which is used during regular data transmission; “fine ranging mode,” which is used to perform fine timing and power offset corrections; and “probing” mode, which is presumably used for estimating the frequency response of the channel, but also is used to further correct the timing and power offsets. The MATLAB model is also capable of simulating the channel impairments a signal may encounter when traversing the upstream channel. Impairments that are specific to individual CMs include integer and fractional timing offsets, micro-reflections, carrier phase offset (CPO), fractional carrier frequency offset (CFO), and network gain/attenuation. Impairments common to all CMs include carrier hum modulation, AM/FM ingress noise, and additive white Gaussian noise (AWGN). It is the hope that the MATLAB scripts that make up the simulation be translated to Verilog HDL to implement the emulator on a field-programmable gate array (FPGA) in the near future. In the event that an FPGA implementation is pursued, research was conducted into designing efficient fractional delay filters (FDFs), which are essential in the simulation of micro-reflections. After performing an FPGA implementation cost analysis between various FDF designs, it was determined that a Kaiser-windowed sinc function FDF with roll-off parameter β = 3.88 was the most cost-efficient choice, requiring at total of 24 multipliers when implemented using an optimized structure.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

The concept of cable television, originally called community antenna television (CATV), began in the 1940's. The information and services provided by cable operators have changed drastically since the early days. Cable service providers are no longer simply providing their customers with broadcast television but are providing a multi-purpose, two-way link to the digital world. Custom programming, telephone service, radio, and high-speed internet access are just a few of the services offered by cable service providers in the 21st century. At the dawn of the internet the dominant mode of access was through telephone lines. Despite advances in dial-up modem technology, the telephone system was unable to keep pace with the demand for data throughput. In the late 1990's an industry consortium known as Cable Television Laboratories, Inc. developed a standard protocol for providing high-speed internet access through the existing CATV infrastructure. This protocol is known as Data Over Cable Service Interface Specification (DOCSIS) and it helped to usher in the era of the information superhighway. CATV systems use different parts of the radio frequency (RF) spectrum for communication to and from the user. The downstream portion (data destined for the user) consumes the bulk of the spectrum and is located at relatively high frequencies. The upstream portion (data destined to the network from the user) of the spectrum is smaller and located at the low end of the spectrum. This lower frequency region of the RF spectrum is particularly prone to impairments such as micro-reflections, which can be viewed as a type of multipath interference. Upstream data transfer in the presence of these impairments is therefore problematic and requires complex signal correction algorithms to be employed in the receiver. The quality of a receiver is largely determined by how well it mitigates the signal impairments introduced by the channel. For this reason, engineers developing a receiver require a piece of equipment that can emulate the channel impairments in any permutation in order to test their receiver. The conventional test methodology uses a hardware RF channel emulator connected between the transmitter and the receiver under test. This method not only requires an expensive RF channel emulator, but a functioning analog front-end as well. Of these two problems, the expense of the hardware emulator is likely less important than the delay in development caused by waiting for a functional analog front-end. Receiver design is an iterative, time consuming process that requires the receiver's digital signal processing (DSP) algorithms be tested as early as possible to reduce the time-to-market. This thesis presents a digital implementation of a DOCSIS-compliant channel emulator whereby cable micro-reflections and thermal noise at the analog front-end of the receiver are modelled digitally at baseband. The channel emulator and the modulator are integrated into a single hardware structure to produce a compact circuit that, during receiver testing, resides inside the same field programmable gate array (FPGA) as the receiver. This approach removes the dependence on the analog front-end allowing it to be developed concurrently with the receiver's DSP circuits, thus reducing the time-to-market. The approach taken in this thesis produces a fully programmable channel emulator that can be loaded onto FPGAs as needed by engineers working independently on different receiver designs. The channel emulator uses 3 independent data streams to produce a 3-channel signal, whereby a main channel with micro-reflections is flanked on either side by adjacent channels. Thermal noise normally generated by the receiver's analog front-end is emulated and injected into the signal. The resulting structure utilizes 43 dedicated multipliers and 401.125 KB of RAM, and achieves a modulation error ratio (MER) of 55.29 dB.

The purpose of this work is to assess and propose possible methods for increasing the transmission speed of the cable television distribution, concretely the UPC network in Brno. The first part of work collectively processes general knowledge and gives the reader into the issue. After that follows an analysis of TV cable networks UPC in Brno, especially view of data transmission. After familiarization with the physical aspect of the network is described data communications itself, including standard DOCSIS, respectively EuroDOCSIS. Particular attention is paid to factors that have effect on data transmission and speed. Benefit is the calculation of dividing ratio in different parts of the network and compared with the real load. As far as possible in the given work results of measurements with regard to the quality of the network. The last part is about how to increase speeds. Perspective solution is mainly a technology which is based on standard EuroDOCSIS 3.0, which introduces the concatenation of individual channels. Result of made tests of first cable modem EuroDOCSIS 3.0 confirms the very high speeds and currently preparedness for other major step in so long development of TV cable network.

There is a growing demand for the high quality TV programs such as High Definition TV (HDTV). The CATV network is often a suitable solution to address this demand using a CATV modem delivering high data rate digital signals in a cost effective manner, thereby, utilizing a complex digital modulation scheme is inevitable. Exploiting complex modulation schemes, entails a more sophisticated modulator and distribution system with much tighter tolerances. However, there are always distortions introduced to the modulated signal in the modulator degrading signal quality.<p> In this research, the effect of distortions introduced by the RF band pass filter in the modulator will be considered which cause degradations on the quality of the output Quadrature Amplitude Modulated (QAM) signal. Since the RF filter's amplitude/group delay distortions are not symmetrical in the frequency domain, once translated into the base band they have a complex effect on the QAM signal. Using Matlab, the degradation effects of these distortions on the QAM signal such as Bit Error Rate (BER) is investigated.<p> In order to compensate for the effects of the RF filter distortions, two different methods are proposed. In the first method, a complex base band compensation filter is placed after the pulse shaping filter (SRRC). The coefficients of this complex filter are determined using an optimization algorithm developed during this research. The second approach, uses a pre-equalizer in the form of a Feed Forward FIR structure placed before the pulse shaping filter (SRRC). The coefficients of this pre-equalizer are determined using the equalization algorithm employed in a test receiver, with its tap weights generating the inverse response of the RF filter. The compensation of RF filter distortions in base band, in turn, improves the QAM signal parameters such as Modulation Error Ratio (MER). Finally, the MER of the modulated QAM signal before and after the base band compensation is compared between the two methods, showing a significant enhancement in the RF modulator performance.

There is a growing demand for the high quality TV programs such as High Definition TV (HDTV). The CATV network is often a suitable solution to address this demand using a CATV modem delivering high data rate digital signals in a cost effective manner, thereby, utilizing a complex digital modulation scheme is inevitable. Exploiting complex modulation schemes, entails a more sophisticated modulator and distribution system with much tighter tolerances. However, there are always distortions introduced to the modulated signal in the modulator degrading signal quality.<p> In this research, the effect of distortions introduced by the RF band pass filter in the modulator will be considered which cause degradations on the quality of the output Quadrature Amplitude Modulated (QAM) signal. Since the RF filter's amplitude/group delay distortions are not symmetrical in the frequency domain, once translated into the base band they have a complex effect on the QAM signal. Using Matlab, the degradation effects of these distortions on the QAM signal such as Bit Error Rate (BER) is investigated.<p> In order to compensate for the effects of the RF filter distortions, two different methods are proposed. In the first method, a complex base band compensation filter is placed after the pulse shaping filter (SRRC). The coefficients of this complex filter are determined using an optimization algorithm developed during this research. The second approach, uses a pre-equalizer in the form of a Feed Forward FIR structure placed before the pulse shaping filter (SRRC). The coefficients of this pre-equalizer are determined using the equalization algorithm employed in a test receiver, with its tap weights generating the inverse response of the RF filter. The compensation of RF filter distortions in base band, in turn, improves the QAM signal parameters such as Modulation Error Ratio (MER). Finally, the MER of the modulated QAM signal before and after the base band compensation is compared between the two methods, showing a significant enhancement in the RF modulator performance.

Approved for public release, distribution is unlimited / Wireless mesh networking has emerged as the successor of the traditional ad hoc networks. New technological advances, the standardization of protocols and interfaces and the maturity of key components have made it possible for current mesh research groups to set goals that are really close to the world's expectations. The objective of this research is to design and implement a simulation toolkit for wireless mesh clusters that can be used as an additional performance evaluation technique for the Tactical Network Topology program of Naval Postgraduate School. This toolkit is implemented in the OPNET simulation environment and it incorporates various nodes running different ad hoc routing protocols. Furthermore, the investigation of a suitable combination of protocols for the Tactical Network Topology is achieved by creating scenarios and running a number of simulations using the mesh toolkit. / Captain, Hellenic Air Force