Return to search

Flip chip assembly process development, process characterization, and reliability assessment of polymer stud grid array-chip scaled package

No description available.
Identiferoai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/19141
Date05 1900
CreatorsPaydenkar, Chetan S.
PublisherGeorgia Institute of Technology
Source SetsGeorgia Tech Electronic Thesis and Dissertation Archive
Detected LanguageEnglish
TypeThesis
RightsAccess restricted to authorized Georgia Tech users only.

Page generated in 0.002 seconds