Conventional solder balls used in microelectronic packaging suffer from thermo- mechanical damage due to difference in coefficient of thermal expansion between the die and the substrate or the substrate and the board. Compliant interconnects are replacements for solder balls which accommodate this differential displacement by mechanically decoupling the die from the substrate or the substrate from the board and aim to improve overall reliability and life of the microelectronic component. Research is being conducted to develop compliant interconnect structures which offer good mechanical compliance without adversely affecting electrical performance, thus obtaining good thermo-mechanical reliability. However, little information is available regarding the behavior of compliant interconnects under shock and impact loads. The objective of this thesis is to study the response of a proposed multi-path compliant interconnect structure when subjected to shock and impact loading. As part of this work, scaled-up substrate-compliant interconnect-die assemblies will be fabricated through stereolithography techniques. These scaled-up prototypes will be subjected to experimental drop testing. Accelerometers will be placed on the board, and strain gauges will be attached to the board and the die at various locations. The samples will be dropped from different heights to different shock levels in the components, according to Joint Electron Devices Engineering Council (JEDEC) standards. In parallel to such experiments with compliant interconnects, similar experiments with scaled-up solder bump interconnects will also be conducted. The strain and acceleration response of the compliant interconnect assemblies will be compared against the results from solder bump interconnects. Simulations will also be carried out to mimic the experimental conditions and to gain a better understanding of the overall response of the compliant interconnects under shock and impact loading. The findings from this study will be helpful for improving the reliability of compliant interconnects under dynamic mechanical loading.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/50132 |
| Date | 27 August 2012 |
| Creators | Bhat, Anirudh |
| Contributors | Sitaraman, Suresh K. |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
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