Address trace compression represents that the address data, which are generated from the instruction fetch stage of the microprocessor, can be retrieved for later observation and analysis. This real time trace compression hardware is the primary component of real-time trace system. In this paper, we present how to design and implement this real-time address trace compressor. Address trace compressor is allowed to perform accurate, successive trace collection in an unlimited length and can be used in various embedded microprocessors without influencing the operation of the microprocessors. Also, it has abundant reconfigurable parameters that can be used to develop a cost-effective trace system. The experiment results show that this compressor can reach a higher compression ratio of 1:100. Hence, by utilizing this real-time compression technique, the trace depths of new trace system can be 20 times more than these existing in-circuit emulators.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0903103-100535 |
| Date | 03 September 2003 |
| Creators | Huang, Shyh-Ming |
| Contributors | Tan-San Wu, Ming-Haw Jing, Kun-Som Cheng, Ing-Jer Huang, Yun-Nan Chang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0903103-100535 |
| Rights | withheld, Copyright information available at source archive |
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