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Modeling, Optimization and Testing for Analog/Mixed-Signal Circuits in Deeply Scaled CMOS Technologies

As CMOS technologies move to sub-100nm regions, the design and verification
for analog/mixed-signal circuits become more and more difficult due to the problems
including the decrease of transconductance, severe gate leakage and profound mismatches.
The increasing manufacturing-induced process variations and their impacts
on circuit performances make the already complex circuit design even more sophisticated
in the deeply scaled CMOS technologies. Given these barriers, efforts are
needed to ensure the circuits are robust and optimized with consideration of parametric
variations. This research presents innovative computer-aided design approaches
to address three such problems: (1) large analog/mixed-signal performance modeling
under process variations, (2) yield-aware optimization for complex analog/mixedsignal
systems and (3) on-chip test scheme development to detect and compensate
parametric failures.
The first problem focus on the efficient circuit performance evaluation with consideration
of process variations which serves as the baseline for robust analog circuit
design. We propose statistical performance modeling methods for two popular
types of complex analog/mixed-signal circuits including Sigma-Delta ADCs and
charge-pump PLLs. A more general performance modeling is achieved by employing
a geostatistics motivated performance model (Kriging model), which is accurate
and efficient for capturing stand-alone analog circuit block performances. Based on the generated block-level performance models, we can solve the more challenging
problem of yield-aware system optimization for large analog/mixed-signal systems.
Multi-yield pareto fronts are utilized in the hierarchical optimization framework so
that the statistical optimal solutions can be achieved efficiently for the systems. We
further look into on-chip design-for-test (DFT) circuits in analog systems and solve
the problems of linearity test in ADCs and DFT scheme optimization in charge-pump
PLLs. Finally a design example of digital intensive PLL is presented to illustrate the
practical applications of the modeling, optimization and testing approaches for large
analog/mixed-signal systems.

Identiferoai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2009-12-7512
Date2009 December 1900
CreatorsYu, Guo
ContributorsLi, Peng
Source SetsTexas A and M University
Languageen_US
Detected LanguageEnglish
TypeBook, Thesis, Electronic Dissertation, text
Formatapplication/pdf

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