As CMOS technologies move to sub-100nm regions, the design and verification for analog/mixed-signal circuits become more and more difficult due to the problems including the decrease of transconductance, severe gate leakage and profound mismatches. The increasing manufacturing-induced process variations and their impacts on circuit performances make the already complex circuit design even more sophisticated in the deeply scaled CMOS technologies. Given these barriers, efforts are needed to ensure the circuits are robust and optimized with consideration of parametric variations. This research presents innovative computer-aided design approaches to address three such problems: (1) large analog/mixed-signal performance modeling under process variations, (2) yield-aware optimization for complex analog/mixedsignal systems and (3) on-chip test scheme development to detect and compensate parametric failures. The first problem focus on the efficient circuit performance evaluation with consideration of process variations which serves as the baseline for robust analog circuit design. We propose statistical performance modeling methods for two popular types of complex analog/mixed-signal circuits including Sigma-Delta ADCs and charge-pump PLLs. A more general performance modeling is achieved by employing a geostatistics motivated performance model (Kriging model), which is accurate and efficient for capturing stand-alone analog circuit block performances. Based on the generated block-level performance models, we can solve the more challenging problem of yield-aware system optimization for large analog/mixed-signal systems. Multi-yield pareto fronts are utilized in the hierarchical optimization framework so that the statistical optimal solutions can be achieved efficiently for the systems. We further look into on-chip design-for-test (DFT) circuits in analog systems and solve the problems of linearity test in ADCs and DFT scheme optimization in charge-pump PLLs. Finally a design example of digital intensive PLL is presented to illustrate the practical applications of the modeling, optimization and testing approaches for large analog/mixed-signal systems.

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies.

En esta tesis se propone un método de diseño para test orientado hacia circuitos mixtos empotrados. El método de test está basado en el análisis del consumo de corriente dinámica (IDDX) tanto estacionaria como transitoria.Con objeto de procesar adecuadamente la información de los transitorios de corriente, la medida se efectúa internamente integrando dentro del chip un bloque sensor de corriente (BICS) junto al circuito bajo test (CUT). Se ha desarrollado una estructura del módulo sensor para otorgar más peso específico al muestreo de las componentes de alta frecuencia de la corriente.El método de test estructural propuesto busca disminuir el tiempo necesario para realizar el test y reducir la complejidad de los equipos de medida comúnmente utilizados en el test analógico. Por ello, el circuito sensor de corriente realiza un procesado de la información para proporcionar una firma digital que codifica el funcionamiento del circuito. La tesis también extiende la propuesta de test a circuitos de capacidades conmutadas (SC) utilizando un circuito sensor de carga integrado junto al circuito bajo test. / This thesis describes a design-for-test method for embedded mixed signal circuits. It is based on the analysis of the dynamic current consumption (IDDX), both quiescent and transient.In order to correctly process the information contained in the transient current, the measurement is performed by a built-in current sensor circuit (BICS) integrated within the circuit under test (CUT). A structure for the sensor block has been developed to give more specific weight to the high-frequency components of the current.The proposed structural test method aims to reduce the test time and the complexity of the measurement equipment commonly used in analog tests. Therefore, the current sensor performs internal data processing to provide a digital signature that encodes the circuit behaviour.The thesis also extends the test method to switched capacitor circuits (SC) using a charge sensor circuit integrated within the circuit under test.

L'expansion du marché des semi-conducteurs dans tous les secteurs d'activité résulte de la capacité de créer de nouvelles applications grâce à l'intégration de plus en plus de fonctionnalités sur une surface de plus en plus faible. Pour chaque entreprise, la compétitivité dépend du coût de fabrication mais aussi de la fiabilité du produit. Ainsi, la phase de test d'un circuit intégré, et plus particulièrement des circuits analogiques et mixtes, est le facteur prédominant dans les choix d'un compromis entre ces deux critères antagonistes, car son coût est désormais proche du coût de production. Cette tendance contraint les acteurs du marché à mettre en place de nouvelles solutions moins onéreuses. Parmi les recherches dans ce domaine, la conception en vue du test (DfT) consiste à intégrer pendant le développement de la puce, une circuiterie additionnelle susceptible d'en faciliter le test, voire d'effectuer un auto-test (BIST). Mais la sélection d'une de ces techniques nécessite une évaluation de leur capacité de différencier les circuits fonctionnels des circuits défaillants. Ces travaux de recherche introduisent une méthodologie d'estimation de la qualité d'une DfT ou d'un BIST dans le flot de conception de circuits analogiques et mixtes. Basée sur la génération d'un large échantillon prenant en compte l'impact des variations d'un procédé technologique sur les performances et les mesures de test du circuit, cette méthodologie calcule les métriques de test exprimant la capacité de chaque technique de détecter les circuits défaillants sans rejeter des circuits fonctionnels et d'accepter les circuits fonctionnels en rejetant les circuits défaillant. Ensuite, le fonctionnement d'un auto-test numérique adapté aux convertisseurs sigma-delta est présenté ainsi qu'une nouvelle méthode de génération et d'injection du stimulus de test. La qualité de ces techniques d'auto-test est démontrée en utilisant la méthodologie d'estimation des métriques de test. Enfin, un démonstrateur développé sur un circuit programmable démontre la possibilité d'employer une technique d'auto-test dans un système de calibrage intégré. / The pervasiveness of the semiconductor industry in an increasing range of applications that span human activity stems from our ability to integrate more and more functionalities onto a small silicon area. The competitiveness in this industry, apart from product originality, is mainly defined by the manufacturing cost, as well as the product reliability. Therefore, finding a trade-off between these two often contradictory objectives is a major concern and calls for efficient test solutions. The focus nowadays is mainly on Analog and Mixed-Signal (AMS) circuits since the associated testing cost can amount up to 70% of the overall manufacturing cost despite that AMS circuits typically occupy no more than 20% of the die area. To this end, there are intensified efforts by the industry to develop more economical test solutions without sacrificing product quality. Design-for-Test (DfT) is a promising alternative to the standard test techniques. It consists of integrating during the development phase of the chip extra on-chip circuitry aiming to facilitate testing or even enable a built-in self-test (BIST). However, the adoption of a DFT technique requires a prior evaluation of its capability to distinguish the functional circuits from the defective ones. In this thesis, we present a novel methodology for estimating the quality of a DfT technique that is readily incorporated in the design flow of AMS circuits. Based on the generation of a large synthetic sample of circuits that takes into account the impact of the process ariations on the performances and test measurements, this methodology computes test metrics that determine whether the DFT technique is capable of rejecting defective devices while passing functional devices. In addition, the thesis proposes a novel, purely digital BIST technique for Sigma-Delta analog-to-digital converters. The efficiency of the test metrics evaluation methodology is demonstrated on this novel BIST technique. Finally, a hardware prototype developed on an FPGA shows the possibility of adapting the BIST technique within a calibration system.

<div>The huge gamut of today’s internet-connected embedded devices has led to increasing concerns regarding the security and confidentiality of data. To address these requirements, most embedded devices employ cryptographic algorithms, which are computationally secure. Despite such mathematical guarantees, as these algorithms are implemented on a physical platform, they leak critical information in the form of power consumption, electromagnetic (EM) radiation, timing, cache hits and misses, and so on, leading to side-channel analysis (SCA) attacks. Non-profiled SCA attacks like differential/correlational power/EM analysis (DPA/CPA/DEMA/CEMA) are direct attacks on a single device to extract the secret key of an encryption algorithm. On the other hand, profiled attacks comprise of building an offline template (model) using an identical device and the attack is performed on a similar device with much fewer traces.</div><div><br></div><div>This thesis focusses on developing efficient side-channel attacks and circuit-level low-overhead generic countermeasures. A cross-device deep learning-based profiling power side-channel attack (X-DeepSCA) is proposed which can break the secret key of an AES-128 encryption engine running on an Atmel microcontroller using just a single power trace, thereby increasing the threat surface of embedded devices significantly. Despite all these advancements, most works till date, both attacks as well as countermeasures, treat the crypto engine as a black box, and hence most protection techniques incur high power/area overheads.</div><div><br></div><div>This work presents the first white-box modeling of the EM leakage from a crypto hardware, leading to the understanding that the critical correlated current signature should not be passed through the higher metal layers. To achieve this goal, a signature attenuation hardware (SAH) is utilized, embedding the crypto core locally within the lower metal layers so that the critical correlated current signature is not passed through the higher metals, which behave as efficient antennas and its radiation can be picked up by a nearby attacker. Combination of the 2 techniques – current-domain signature suppression and local lower metal routing shows >350x signature attenuation in measurements on our fabricated 65nm test chip, leading to SCA resiliency beyond 1B encryptions, which is a 100x improvement in both EM and power SCA protection over the prior works with comparable overheads. Moreover, this is a generic countermeasure and can be utilized for any crypto core without any performance degradation.</div><div><br></div><div>Next, backed by our physics-level understanding of EM radiation, a digital library cell layout technique is proposed which shows >5x reduction in EM SCA leakage compared to the traditional digital logic gate layout design. Further, exploiting the magneto-quasistatic (MQS) regime of operation for the present-day CMOS circuits, a HFSS-based framework is proposed to develop a pre-silicon EM SCA evaluation technique to test the vulnerability of cryptographic implementations against such attacks during the design phase itself.</div><div><br></div><div>Finally, considering the continuous growth of wearable and implantable devices around a human body, this thesis also analyzes the security of the internet-of-body (IoB) and proposes electro-quasistatic human body communication (EQS-HBC) to form a covert body area network. While the traditional wireless body area network (WBAN) signals can be intercepted even at a distance of 5m, the EQS-HBC signals can be detected only up to 0.15m, which is practically in physical contact with the person. Thus, this pioneering work proposing EQS-HBC promises >30x improvement in private space compared to the traditional WBAN, enhancing physical security. In the long run, EQS-HBC can potentially enable several applications in the domain of connected healthcare, electroceuticals, augmented and virtual reality, and so on. In addition to these physical security guarantees, side-channel secure cryptographic algorithms can be augmented to develop a fully secure EQS-HBC node.</div>