The scaling of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) has continued for over four decades, providing device performance gains and considerable economic benefits. However, continuing this scaling trend is being impeded by the increase in dissipated power. Considering the exponential increase of the number of transistors per unit area in high speed processors, the power dissipation has now become the major challenge for device scaling, and has led to tremendous research activity to mitigate this issue, and thereby extend device scaling limits. In such efforts, non-planar device structures, high mobility channel materials, and devices operating under different physics have been extensively investigated. Non-planar device geometries reduce short-channel effects by enhancing the electrostatic control over the channel. The devices using high mobility channel materials such as germanium (Ge), SiGe, and III-V can outperform Si MOSFETs in terms of switching speed. Tunneling field-effect transistors use interband tunneling of carriers rather than thermal emission, and can potentially realize low power devices by achieving subthreshold swings below the thermal limit of 60 mV/dec at room temperature. In this work, we examine two device options which can potentially provide high switching speed combined with reduced power, namely germanium nanowire (NW) field-effect transistors (FETs) and tunneling field-effect transistors (TFETs). The devices use germanium (Ge) – silicon-germanium (Si[subscript x]Ge[subscript 1-x]) core-shell nanowires (NWs) as channel material for the realization of the devices, synthesized using a 'bottom-up' growth process. The device design and material choice are motivated by enhanced electrostatic control in the cylindrical geometry, high hole mobility, and lower bandgap by comparison to Si. We employ low energy ion implantation of boron and phosphorous to realize highly doped contact regions, which in turn provide efficient carrier injection. Our Ge-Si[subscript x]Ge[subscript 1-x] core-shell NW FETs and NW TFETs were fabricated using a conventional CMOS process and their electrical properties were systematically characterized. In addition, TCAD (Technology computer-aided design) simulation is also employed for the analysis of the devices. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/ETD-UT-2010-12-2268 |
| Date | 07 February 2011 |
| Creators | Nah, Junghyo, 1978- |
| Source Sets | University of Texas |
| Language | English |
| Detected Language | English |
| Type | thesis |
| Format | application/pdf |
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