We design the microarchitecture of the Multi-Level Computing Architecture (MLCA),
focusing on its Control Processor (CP). The design of the microarchitecture of the CP
faces us with both opportunities and challenges that stem from the coarse granularity of
the tasks and the large number of inputs and outputs for each task instruction. Thus,
we explore changes to standard superscalar microarchitectural techniques. We design
the entire CP microarchitecture and implement it on an FPGA using SystemVerilog.
We synthesize and evaluate the MLCA system based on a 4-processor shared-memory
multiprocessor. The performance of realistic applications shows scalable speedups that
are comparable to that of simulation. We believe that our implementation achieves low
complexity in terms of FPGA resource usage and operating frequency. In addition, we
argue that our design methodology allows the scalability of the CP as the entire system
grows.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/11134 |
| Date | 30 July 2008 |
| Creators | Capalija, Davor |
| Contributors | Abdelrahman, Tarek S. |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
| Format | 1141144 bytes, application/pdf |
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