PhD Thesis / Recently, gallium nitride high electron mobility transistor [GaN HEMT] has evolved as a promising device in the field of power electronics. It has excellent material qualities such as high bandgap, high saturation velocity, and good thermal stability which is expected to give superior device performances compared to its Si counterparts. One of the major challenges in GaN technology is to achieve enhancement operation (or normally off mode) due to the presence of its inherent two-dimensional electron gas[2DEG]. Among many methods developed to realize this, pGaN HEMT has emerged as the most encouraging technique for power GaN technology due to its high threshold voltage and good reliability. However, one of the major issues in pGaN HEMTs is that it suffers from high gate leakage current which limits their device performance. In this thesis, we have made a detailed study of the gate leakage process in pGaN HEMTs in terms of modeling, TCAD simulations, and alternative methods being used to reduce gate leakage in pGaN devices.
A numerical model has been developed to model the gate leakage in pGaN HEMTs as a function of gate bias and temperature. This model is validated against 5 devices with different contact metals, geometries, and process conditions. A single model with a consistent set of parameters can fit the experimental data for all these 5 devices without the need to invoke multiple mechanisms to explain the gate leakage process.
The numerical model relied on some simplifications, such as ignoring series resistance, using the compact diode model, and using a simplified expression to describe trap-assisted tunneling. Using commercial TCAD simulations, can address these limitations since the simulator computes the electric field distribution throughout the structure. Furthermore, using TCAD some of the trap levels have been identified which accounts for leakage at low bias. We were able to calibrate our TCAD simulations against published data for the drain current and then used the calibrated simulation environment to accurately simulate gate leakage using parameters that closely correspond to the physical phenomena described, including interface trap parameters, which we identify with known trap levels in GaN.
Finally, we have examined different strategies that have been implemented so far to reduce leakage current. The pGaN layer is important in the whole device operation. Its doping concentration and thickness affect the leakage characteristics. Three modified structures have been studied through TCAD simulations which decrease gate leakage current. In each case, we used our calibrated TCAD model to study the impact on the drain current as well as the leakage current. Our results closely fit published experimental results and therefore provide confidence on the simulated dependence of leakage and drive current behavior on process modifications. The specific results, and our model overall, are expected to be of benefit to device designers in optimizing device structures for leakage while maintaining the required drive current. / Thesis / Doctor of Philosophy (PhD)
| Identifer | oai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/28181 |
| Date | January 2022 |
| Creators | Sarkar, Arghyadeep |
| Contributors | Haddara, Yaser, Electrical and Computer Engineering |
| Source Sets | McMaster University |
| Language | English |
| Detected Language | English |
| Type | Thesis |
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