For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (TSV). This technology increases the effective area of the MEMS device by elimination dead space, which is typically required for other approaches based on wire bond assembly. Within this thesis, different TSV technology concepts with respect to a 3D-WLP for MEMS have been developed. Thereby, the focus was on a copper based technology as well as on two major TSV implementation methods. This comprises a Via Middle approach based on the separated TSV fabrication in the cap wafer as well as a Via Last approach with a TSV implementation in either the MEMS or cap wafer, respectively. For each option with its particular challenges, corresponding process modules have been developed. In the Via Middle approach, the wafer-related etch rate homogeneity determines the TSV reveal from the wafer backside Here, a reduction of the TSV depth down to 80 μm is favourable as long as the desired Cu-thermo-compression bonding (Cu-TCB) is performed before the thinning. For the TSV metallisation, a Cu electrochemical deposition method was developed, which allows the deposition of one redistribution layer as well as the bonding patterns for Cu-TCB at the same time. In the Via Last approach, the TSV isolation represents one challenge. Chemical Vapour Deposition processes have been investigated, for which a combination of PE-TEOS and SA-TEOS as well as a Parylene deposition yield the most promising results. Moreover, a method for the realisation of a suitable bonding surface for the Silicon Direct Bonding method has been developed, which does not require any wet pre treatment of the fabricated MEMS patterns. A functional MEMS acceleration sensor as well as Dummy devices serve as demonstrators for the overall integration technology as well as for the characterisation of electrical parameters.:Bibliographische Beschreibung 3
Vorwort 13
List of symbols and abbreviations 15
1 Introduction 23
2 Fundamentals on MEMS and TSV based 3D integration 25
2.1 Micro Electro-Mechanical systems 25
2.1.1 Basic Definition 25
2.1.2 Silicon technologies for MEMS 26
2.1.3 MEMS packaging 29
2.2 3D integration based on TSVs 33
2.2.1 Overview 33
2.2.2 Basic processes for TSVs 34
2.2.3 Stacking and Bonding 47
2.2.4 Wafer thinning 48
2.3 TSV based MEMS packaging 50
2.3.1 MEMS-TSVs 50
2.3.2 3D-WLP for MEMS 52
3 Technology development for a 3D-WLP based MEMS 57
3.1 Target integration approach for 3D-WLP based MEMS 57
3.1.1 MEMS modules using 3D-WLP based MEMS 57
3.1.2 Integration concepts 58
3.2 Objective and requirements for the proposed 3D-WLP of MEMS 60
3.2.1 Boundary conditions 60
3.2.2 Technology concepts 63
3.3 Selected approaches for TSV implementation in MEMS 64
3.3.1 Via Last Technology 64
3.3.2 Via Middle technology 69
4 Development of process modules 75
4.1 Characterisation 75
4.2 TSV related etch processes 77
4.2.1 Equipment 77
4.2.2 Deep silicon etching 78
4.2.3 Etching of the buried dielectric layer 84
4.2.4 Patterning of TSV isolation liner – spacer etching 90
4.2.5 Summary 92
4.3 TSV isolation 93
4.3.1 Principle considerations 93
4.3.2 Experiment 95
4.3.3 Results 97
4.3.4 Summary 102
4.4 Metallisation of TSV and RDL 103
4.4.1 Plating base and experimental setup 103
4.4.2 Investigations related to the ECD process 106
4.4.3 Pattern plating 117
4.4.4 Summary 123
4.5 Wafer Level Bonding 124
4.5.1 Silicon direct bonding 124
4.5.2 Thermo-compression bonding by using ECD copper 128
4.5.3 Summary 134
4.6 Wafer thinning and TSV back side reveal 134
4.6.1 Thinning processes 134
4.6.2 TSV reveal processes 136
4.6.3 Summary 145
4.7 Under bump metallisation and solder bumps 146
5 Demonstrator design, fabrication and characterisation 149
5.1 Single wafer demonstrator for electrical test 149
5.1.1 Demonstrator design and test structure layout 149
5.1.2 Demonstrator fabrication 150
5.1.3 Electrical measurement 151
5.1.4 Summary 153
5.2 Via Last based TSV fabrication in the MEMS device wafer 153
5.2.1 Layout of the MEMS device with TSVs 153
5.2.2 Fabrication of TSVs and wafer thinning 154
5.2.3 Characterisation of the fabricated device 155
5.2.4 Summary 156
5.3 Via Last based cap-TSV for very thin MEMS devices 157
5.3.1 Design 157
5.3.2 Fabrication 158
5.3.3 Characterisation 161
5.3.4 Summary 162
5.4 Via Middle approach based on thinning after bonding 163
5.4.1 Design 163
5.4.2 Results and characterisation 164
5.4.3 Summary 166
6 Conclusion and outlook 167
Appendix A: Typical requirements on a MEMS package and its functions 171
Appendix B: Classification of packaging and system integration techniques 173
B.1 Packaging of electronic devices in general 173
B.2 Single Chip Packages 174
B.3 System integration 175
B.4 3D integration based on TSVs 180
Bibliography 183
List of figures 193
List of tables 199
Versicherung 201
Theses 203
Curriculum vitae 205
Own publications 207 / Im Bereich mobiler Elektronik, wie z.B. bei Smartphones, Smartcards oder in Kleidung integrierten Geräten ist ein Trend zu erkennen hinsichtlich steigender Funktionalität und Miniaturisierung. Bei dieser Entwicklung spielen Mikroelektromechanische Systeme (MEMS) eine entscheidende Rolle zur Realisierung neuer Funktionen, wie z.B. der Bewegungsdetektion. Die Anforderungen derartiger Bauteile zusammen mit dem begrenzten zur Verfügung stehenden Platz erfordern neuartige Technologien für die Aufbau- und Verbindungstechnick (engl. Packaging) der Bauteile. Das 3D-Wafer Level Packaging (3D-WLP) ermöglicht eine Lösung für eine miniaturisierte MEMS-Bauform unter Nutzung von Techniken wie dem Waferlevelbonden (WLB) und den Siliziumdurchkontaktierungen (TSV von engl. Through Silicon Via). Diese Technologie erhöht die effektive aktive Fläche des MEMS Bauteils durch die Reduzierung von Toträumen, welche für andere Ansätze wie der Drahtbond-Montage üblich sind. In der vorliegenden Arbeit wurden verschiedene Technologiekonzepte für den Aufbau von 3D-WLP für MEMS erarbeitet. Dabei lag der Fokus auf einer Kupfer-basierten Technologie sowie auf zwei prinzipiellen Varianten für die TSV-Implementierung. Dies umfasst den Via Middle Ansatz, welcher auf der TSV Herstellung auf einem separaten Kappenwafer beruht, sowie den Via Last Ansatz mit einer TSV Herstellung entweder im MEMS-Wafer oder im Kappenwafer. Für beide Varianten mit individuellen Herausforderungen wurden entsprechende Prozessmodule entwickelt. Beim Via Middle Ansatz ist die Wafer-bezogene Ätzratenhomogenität des Siliziumtiefenätzen entscheidend für das spätere Freilegen der TSVs von der Rückseite. Hier hat sich eine Reduzierung der TSV-Tiefe auf bis zu 80 μm vorteilhaft erwiesen insofern, das Kupfer-Thermokompressionsbonden (Cu-TKB) vor dem Abdünnen erfolgt. Zur Metallisierung der TSVs wurde ein Cu Galvanikprozess erarbeitet, welcher es ermöglicht gleichzeitig eine Umverdrahtungsebene sowie die Bondstrukturen für das Cu-TKB zu erzeugen. Beim Via Last Ansatz ist die TSV Isolation eine Herausforderung. Es wurden CVD (Chemische Dampfphasenabscheidung) Prozesse untersucht, wobei eine Kombination aus PE-TEOS und SA-TEOS sowie eine Parylene Beschichtung erfolgversprechende Ergebnisse liefern. Des Weiteren wurde eine Methode zur Erzeugung bondfähiger Oberflächen für das Siliziumdirektbonden erarbeitet, welche eine Nass-Vorbehandlung des MEMS umgeht. Ein realer MEMS-Beschleunigungssensor sowie Testaufbauten dienen zur Demonstration der Gesamtintegrationstechnologie sowie zur Charakterisierung elektrischer Parameter.:Bibliographische Beschreibung 3
Vorwort 13
List of symbols and abbreviations 15
1 Introduction 23
2 Fundamentals on MEMS and TSV based 3D integration 25
2.1 Micro Electro-Mechanical systems 25
2.1.1 Basic Definition 25
2.1.2 Silicon technologies for MEMS 26
2.1.3 MEMS packaging 29
2.2 3D integration based on TSVs 33
2.2.1 Overview 33
2.2.2 Basic processes for TSVs 34
2.2.3 Stacking and Bonding 47
2.2.4 Wafer thinning 48
2.3 TSV based MEMS packaging 50
2.3.1 MEMS-TSVs 50
2.3.2 3D-WLP for MEMS 52
3 Technology development for a 3D-WLP based MEMS 57
3.1 Target integration approach for 3D-WLP based MEMS 57
3.1.1 MEMS modules using 3D-WLP based MEMS 57
3.1.2 Integration concepts 58
3.2 Objective and requirements for the proposed 3D-WLP of MEMS 60
3.2.1 Boundary conditions 60
3.2.2 Technology concepts 63
3.3 Selected approaches for TSV implementation in MEMS 64
3.3.1 Via Last Technology 64
3.3.2 Via Middle technology 69
4 Development of process modules 75
4.1 Characterisation 75
4.2 TSV related etch processes 77
4.2.1 Equipment 77
4.2.2 Deep silicon etching 78
4.2.3 Etching of the buried dielectric layer 84
4.2.4 Patterning of TSV isolation liner – spacer etching 90
4.2.5 Summary 92
4.3 TSV isolation 93
4.3.1 Principle considerations 93
4.3.2 Experiment 95
4.3.3 Results 97
4.3.4 Summary 102
4.4 Metallisation of TSV and RDL 103
4.4.1 Plating base and experimental setup 103
4.4.2 Investigations related to the ECD process 106
4.4.3 Pattern plating 117
4.4.4 Summary 123
4.5 Wafer Level Bonding 124
4.5.1 Silicon direct bonding 124
4.5.2 Thermo-compression bonding by using ECD copper 128
4.5.3 Summary 134
4.6 Wafer thinning and TSV back side reveal 134
4.6.1 Thinning processes 134
4.6.2 TSV reveal processes 136
4.6.3 Summary 145
4.7 Under bump metallisation and solder bumps 146
5 Demonstrator design, fabrication and characterisation 149
5.1 Single wafer demonstrator for electrical test 149
5.1.1 Demonstrator design and test structure layout 149
5.1.2 Demonstrator fabrication 150
5.1.3 Electrical measurement 151
5.1.4 Summary 153
5.2 Via Last based TSV fabrication in the MEMS device wafer 153
5.2.1 Layout of the MEMS device with TSVs 153
5.2.2 Fabrication of TSVs and wafer thinning 154
5.2.3 Characterisation of the fabricated device 155
5.2.4 Summary 156
5.3 Via Last based cap-TSV for very thin MEMS devices 157
5.3.1 Design 157
5.3.2 Fabrication 158
5.3.3 Characterisation 161
5.3.4 Summary 162
5.4 Via Middle approach based on thinning after bonding 163
5.4.1 Design 163
5.4.2 Results and characterisation 164
5.4.3 Summary 166
6 Conclusion and outlook 167
Appendix A: Typical requirements on a MEMS package and its functions 171
Appendix B: Classification of packaging and system integration techniques 173
B.1 Packaging of electronic devices in general 173
B.2 Single Chip Packages 174
B.3 System integration 175
B.4 3D integration based on TSVs 180
Bibliography 183
List of figures 193
List of tables 199
Versicherung 201
Theses 203
Curriculum vitae 205
Own publications 207
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:20832 |
| Date | 29 November 2017 |
| Creators | Hofmann, Lutz |
| Contributors | Schulz, Stefan E., Gerlach, Gerald, Technische Universität Chemnitz |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
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