In this paper, we propose a novel Unipolar CMOS device in which the transport carriers are electron only. And we achieve good inverter output waveform and logic circuit applications by simulation. Duo to all n-channel (NMOS) structures are used, we call this proposed CMOS as a Unipolar CMOS. A new basic theory of utilizing the punch through effect is
demonstrated to enhance the tPLH in our proposed Unipolar CMOS. The average delay time compared with the classical CMOS circuit can be improved 23% for high-performance applications. For our proposed Unipolar CMOS, all n-channel MOS are used to eliminate the N- and P-well processes and ignore the difference between the carrier mobility. In addition, the common electrodes are also exploited, hence, the layout area can be reduced to about 75%, which leads to significantly increase the packing density of CMOS circuits in the same chip.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0730110-150123 |
| Date | 30 July 2010 |
| Creators | Sun, Chih-hung |
| Contributors | Yao-Tsung Tsai, Wen-Kuan Yeh, Meng-Hsueh Chiang, Jyi-Tsong Lin, Albert Chin |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730110-150123 |
| Rights | not_available, Copyright information available at source archive |
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