Photolithography is the most complex of the operations involved in the fabrication of a wafer, and it requires the greatest precision. Photolithography is used to create multiple layers of circuit patterns on a chip. Traditionally, wafer fab operations, and in particular, those performed in the photolithography processing area, have always presented challenging scheduling and control problems. Some of the characteristics that make the photolithography processing area difficult to schedule are as follows: reentrant flow, unpredictable yield and rework time at critical operations, shared resources such as reticles, rapidly changing technologies, and lot dedication for steppers and scanners for critical layers. This processing area, where wafers are exposed using scanners or steppers, typically, comprises the bottleneck workstations. Also, the numbers of reticles available for a given layer of product type are limited. Consequently, it is important to develop appropriate schedules to ensure effective utilization of the tools involved.
In this study, a manufacturing line that is used to produce four dynamic random access memory (DRAM) products, requiring approximately 240 stages with 18 photolithography layers, is considered. The problem we propose to investigate can concisely be described as follows: Given a set of products to be processed in a photolithography area consisting of steppers and scanners (tools), with each product requiring a specific reticle type, determine the sequence in which to process the lots on the tools loaded with requisite reticles, so as to minimize the cycle time. The reticles required for processing a product are known apriori and can be transferred from one tool to another. Also, the lot dedication requirement has to be met. This requirement pertains to the fact that some of the layers of a lot should be processed on the same tool. (Scanner or Stepper). The processing of other layers may not require lot dedication. These are handled accordingly. Some lots may enter into the system with the requirement of processing them urgently. (called hot lots). These are handled in the formulation of the problem as such.
Two solution methodologies are presented for the above stated problem. The first methodology uses a mathematical programming based approach. For the given routes and processing times of the product types, the entire problem is formulated as an Integer program. This integer program uses the start time of the jobs at various operations and the availability of reticles as variables, among others. The objective is to reduce the cycle time of the lots released into the system. The cycle time of a lot is defined as the time that a lot spends in the system. Results from the experimentation for integer program show that the computation time for solving small size problems is very high. A methodology is presented to solve this model efficiently.
The second methodology consists of the development of a new dispatching rule for scheduling lots in the photolithography processing area. This along with the other dispatching rules discussed in the literature are implemented using the Autosched AP software to study the impact that lot dedication makes on the performance of a fab. The performance measures that are considered include throughput, cycle time, WIP and utilization of tool sets. The results are presented for 1-level, 2-level and 3-level lot dedication schemes. . It is shown that the 3- level lot dedication scheme performs the best under no preventive maintenance/breakdown case while, for the deterministic value of unscheduled breakdown times and preventive maintenance schedule used, 1-level lot dedication performed the best. Even though the 3-level lot dedication scheme is more flexible as compared to the 1–level lot dedication scheme, yet for the values of unscheduled breakdown times and preventive maintenance schedule used, the performance of the 3- level lot dedication scheme is worse than that of the 1- level lot dedication scheme. For another set of break down time values and preventive maintenance schedule, the outcome can be different. We also compare the performance of the proposed procedure with that of the dispatching rules available with the AutoSched AP software. The results indicate that the proposed procedure is consistent in generating better solutions under different operating conditions. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/30786 |
| Date | 09 January 2003 |
| Creators | Kidambi, Madhav |
| Contributors | Industrial and Systems Engineering, Sarin, Subhash C., Laman, Denise, Burchin, Yossi |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | Thesis0107.pdf |
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