Photolithography is the most complex of the operations involved in the fabrication of a wafer, and it requires the greatest precision. Photolithography is used to create multiple layers of circuit patterns on a chip. Traditionally, wafer fab operations, and in particular, those performed in the photolithography processing area, have always presented challenging scheduling and control problems. Some of the characteristics that make the photolithography processing area difficult to schedule are as follows: reentrant flow, unpredictable yield and rework time at critical operations, shared resources such as reticles, rapidly changing technologies, and lot dedication for steppers and scanners for critical layers. This processing area, where wafers are exposed using scanners or steppers, typically, comprises the bottleneck workstations. Also, the numbers of reticles available for a given layer of product type are limited. Consequently, it is important to develop appropriate schedules to ensure effective utilization of the tools involved. In this study, a manufacturing line that is used to produce four dynamic random access memory (DRAM) products, requiring approximately 240 stages with 18 photolithography layers, is considered. The problem we propose to investigate can concisely be described as follows: Given a set of products to be processed in a photolithography area consisting of steppers and scanners (tools), with each product requiring a specific reticle type, determine the sequence in which to process the lots on the tools loaded with requisite reticles, so as to minimize the cycle time. The reticles required for processing a product are known apriori and can be transferred from one tool to another. Also, the lot dedication requirement has to be met. This requirement pertains to the fact that some of the layers of a lot should be processed on the same tool. (Scanner or Stepper). The processing of other layers may not require lot dedication. These are handled accordingly. Some lots may enter into the system with the requirement of processing them urgently. (called hot lots). These are handled in the formulation of the problem as such. Two solution methodologies are presented for the above stated problem. The first methodology uses a mathematical programming based approach. For the given routes and processing times of the product types, the entire problem is formulated as an Integer program. This integer program uses the start time of the jobs at various operations and the availability of reticles as variables, among others. The objective is to reduce the cycle time of the lots released into the system. The cycle time of a lot is defined as the time that a lot spends in the system. Results from the experimentation for integer program show that the computation time for solving small size problems is very high. A methodology is presented to solve this model efficiently. The second methodology consists of the development of a new dispatching rule for scheduling lots in the photolithography processing area. This along with the other dispatching rules discussed in the literature are implemented using the Autosched AP software to study the impact that lot dedication makes on the performance of a fab. The performance measures that are considered include throughput, cycle time, WIP and utilization of tool sets. The results are presented for 1-level, 2-level and 3-level lot dedication schemes. . It is shown that the 3- level lot dedication scheme performs the best under no preventive maintenance/breakdown case while, for the deterministic value of unscheduled breakdown times and preventive maintenance schedule used, 1-level lot dedication performed the best. Even though the 3-level lot dedication scheme is more flexible as compared to the 1–level lot dedication scheme, yet for the values of unscheduled breakdown times and preventive maintenance schedule used, the performance of the 3- level lot dedication scheme is worse than that of the 1- level lot dedication scheme. For another set of break down time values and preventive maintenance schedule, the outcome can be different. We also compare the performance of the proposed procedure with that of the dispatching rules available with the AutoSched AP software. The results indicate that the proposed procedure is consistent in generating better solutions under different operating conditions. / Master of Science

The semiconductor industry provides a host of very challenging problems in production planning and scheduling because of the unique features of the wafer fab. This research addresses the need to develop an approach, which can be used to generate optimal or near-optimal solutions to the scheduling problem of a wafer fab, by using Mathematical Programming for a general case of a wafer fab. The problem is approached in two steps. First, the number of lots of different products to be released into the system during each planning period is determined, such that the total tardiness of the product orders is minimized over the planning horizon. Second, the schedule of these lots is determined so that the cycle time of each lot released into the system is minimized. Thus, the performance measures based both on due dates and cycle time are considered. The lot release, tardiness problem is formulated as an integer linear program, and a 3-phase procedure, which utilizes a variation of the Wilkerson-Irwin algorithm, is developed. The performance of this 3-phase procedure is further improved by using insights from classical scheduling theory. The scheduling problem is formulated as a 0-1 integer linear program. An algorithm is developed for tightening the LP relaxation of this 0-1 integer linear programming model (of the scheduling problem) leading to a better performance of the branch and bound procedure used for its solution. Lagrangian relaxation is applied on a carefully chosen set of constraints in the scheduling problem, and a Lagrangian heuristic is developed for scheduling the jobs in each period of the planning horizon. Several useful insights are developed throughout to further improve the performance of the proposed algorithm. Experiments are conducted for both the tardiness and the scheduling problems. Five experiments are conducted for the tardiness problem. Each experiment has a different combination of number of products, machines, and work orders in a small sized wafer fab (2 to 6 products, 8 to 10 station families, 15 to 30 workstations, 9 to19 work orders, and 100 to 250 lots per work order). The solutions obtained by the 3-phase procedure are compared to the optimal solutions of the corresponding tardiness problems, and the tardiness per work order for the 3-phase procedure is 0% to 25% greater than the optimal solution. But the time required to obtain the optimal solution is 22 to 1074 times greater than the time required to obtain the solution through the 3-phase procedure. Thus, the 3-phase procedure can generate almost optimal solutions and requires much smaller computation time than that required by the optimal solution. Four experiments are conducted to test the performance of the scheduling problem. Each experiment has a different combination of number of products, machines, routes, bottleneck stations, processing times, and product mix entering the system each day in a small sized wafer fab (2 products, 8 station families, 18 workstations, and 8 to 10 lots released per day into the system). The solution quality of the schedule generated by the Lagrangian heuristic is compared to the solution provided by the standard dispatching rules available in practice. In each experiment, the cycle time of a product for each dispatching rule is divided by the best cycle time for that product over all the dispatching rules in that experiment. This ratio for the Lagrangian heuristic in each experiment and over all the experiments varies from 100% to 104%. For the standard dispatching rules, this ratio ranges from 100% to 120% in each experiment and also over all the experiments. The average of the ratio over all the experiments is the least for the Lagrangian heuristic. This indicates that for the experiments conducted, the Lagrangian heuristic consistently provides a solution that is, or is close to, the best solution and, hence, quite competitive when compared to the standard dispatching rules. / Master of Science

Future 450mm semiconductor wafer foundries are expected to produce billions of low cost, leading-edge processors, memories, and wireless sensors for Internet of Everything applications in smart cities, smart grids, and smart infrastructures. The problem has been a lack of wise investment decision making using traditional semiconductor industry models. The purpose of this study was to design decision-making models to conserve financial resources from conception to commercialization using real options to optimize production capacity, to defer an investment, and to abandon the project. The study consisted of 4 research questions that compared net present value from real option closed-form equations and binomial lattice models using the Black-Scholes option pricing theory. Three had focused on sensitivity parameters. Moore's second law was applied to find the total foundry cost. Data were collected using snowball sampling and face-to-face surveys. Original survey data from 46 Americans in the U.S.A. were compared to 46 Europeans in Germany. Data were analyzed with a paired-difference test and the Box-Behnken design was employed to create prediction models to support each hypothesis. Data from the real option models and survey findings indicate American 450mm foundries will likely capture greater value and will choose the differentiation strategy to produce premium chips, whereas higher capacity, cost leadership European foundries will produce commodity chips. Positive social change and global quality of life improvements are expected to occur by 2020 when semiconductors will be needed for the $14 trillion Internet of Everything market to create safe self-driving vehicles, autonomous robots, smart homes, novel medical electronics, wearable computers with streaming augmented reality information, and digital wallets for cashless societies.

Since 1970s, ever growing attention has been devoted by worldwide researchers and practitioners to the investigation of job release control. However, the need for control of flow of job/wafer into the wafer fabrication system is identified in the late 1988s. Subsequently, many release policies are developed and presented in the literature for improving its performance with respect to cycle time and throughput. Even though it is pointed out in the literature that there is a need for the development and analysis of policy that control the flow of job/wafer through the manufacturing process, still there is no exhaustive study in view of the previously developed release policies in the literature. Moreover, many new opportunities have evolved in the field of release policy in wafer fabrication industry due to the advancement in technology and computer science. It implies that near real-time decision making for efficient release policy is possible based on the global factory state. However, it appears from the literature that still to date the release policies, which are employed in real wafer fabrication system, are usually based on the static information. Release control/policy is emerging as an important research topic in the wafer fabrication industry given the extremely large capital investment and sales revenue of this industry. Release policy also hold practical significance for manufacturing managers, since neglecting it can lead to wide variations in shop workloads, can cause excessive backlogs, accomplishment of orders will be either too early or too late and there can be frequent need for expediting. All the challenges associated with the performance of the wafer fabrication system discussed here and the puzzle around the release policies and its impact on the wafer fabrication process, this research attempts to investigate existing release policies and proposing a few efficient release policies based on the knowledge gained from the existing release policies strength and weakness. Based on the insights gained from the existing release policies, three new closed loop release policies constant workload (CONSTWL), constant batch machine workload (CONSTBWL) and layer wise control (LWC) are developed by considering the parameters: workload in general, workload in batch machine, and re-entrant characteristics of the wafer fabrication system respectively. The conceptual significance in favour of these proposed closed loop release policies in improving performance of the wafer fabrication system is also outlined in this study. In the literature, few researchers clearly indicate that dispatching rule(s) influence the performance of wafer fabrication system either independently or in integration with release policies. Therefore, to empirically validate this fact, release policy is integrated with dispatching rule particularly applying on bottleneck (discrete processing machine) work station in this study. With these, the aims of proposed release policies are to efficiently improve the system performances in terms of average cycle time, standard deviation of cycle time and throughput. Accordingly, a simulation model is proposed and developed using Arena software for evaluating the performance of release policies in integration with dispatching rule applied on bottleneck work station in wafer fabrication environment. Further, to set the values of parameters in the simulation model, the cause and effect analysis is explored in this study by considering eight critical parameters or factors of the simulated wafer fabrication environment. It includes arrival rate, arrival distribution, processing time, maintenance schedule, operator’s schedule, batch size, dispatching rule and release policy. Simulation based cause and effect analysis not only helps in setting up the values of parameters in the proposed simulation model, but it also helps in strengthening the face validity of the developed simulation model. The verification and validation of the developed simulation model, which is a vital and fundamental aspect of simulation is discussed in detail in this study. Based on the analysis and the results observed from the cause and effect analysis, some modifications are incorporated and subsequently, the parameters values are set in the proposed simulation model for evaluating the performance of release policies integrating with dispatching rules. A series of simulation experiments are conducted using the proposed simulation model with systems conditions such as product mix, complexity of the process, level of machine unreliability, and system congestion level to study the relative effects of each of 18 release policies (one open loop release policy, 14 existing closed loop release policies, and 3 proposed release policies) in integration with dispatching rules (FIFO, LIFO and SRPT), considered in this study, at various throughput levels in the wafer fabrication environment. Particularly, the relative effect of integrating release policies and the dispatching rules are observed and analysed in terms of (a) the effect of dispatching rule on release policy, and (b) the effects of release policies on dispatching rules. It is observed from the overall inferences that dispatching rule: SRPT outperformed both FIFO and LIFO dispatching rule for all the considered release policies, except for the release policy: ‘TOTAL_CT’. Additionally, it is observed that for each of the eighteen release policies integrated with considered, the dispatching rule: SRPT produces less WIP inventory at the bottleneck work station for all throughput levels. The maximum deviation in delay (cycle time) is produced by dispatching rule: LIFO in all the release policies considered except for the release policy: ‘TOTAL_CT’ in which dispatching rule: SRPT produces maximum deviation in delay. Moreover, it is observed that the difference in mean delay with all three dispatching rules (FIFO, LIFO and SRPT) increases with the increase in throughput levels. Furthermore, it is observed that the throughput rate under all release policies (except ‘TOTAL_CT’) is more for dispatching rule: SRPT in comparison with both dispatching rules: FIFO and LIFO for nearly the same threshold values. The experimental results showed that proposed release policy: LWC reliably improves the system performance followed by the proposed release policy: CONSTWL and CONSTBWL with respect to both mean delay and standard deviation for corresponding throughput levels in wafer fabrication system. The characteristics of the proposed release policy: LWC are summarized and the same is presented as follows because this is proven to be best release policy among all the release policies considered in the proposed simulation model. The proposed release policy: LWC is a new measure of the work quantity on the shop floor system, which takes into account the location of jobs/wafers along the production line by employing re-entrant property of wafer fabrication system. As a result, it offers quick response to the stochastic events of the manufacturing system and can compensated the system disturbances in time. The proposed release policy: LWC offers more efficient control of flow of job/wafer in the wafer fabrication system with reduced delay (cycle time) and the standard deviation of delay (cycle time) for a given throughput level in comparison with almost all the release policies considered in this study in integration with all three dispatching rules considered and applied on bottleneck work station. For instance, from the analysis of simulation model, the proposed release policy: LWC reduces the average delay up to 98%, 95%, 90%, 89%, 49%, 35%, 21%, 17%, 13%, 12%, 10%, 9%, 9%, 9%, 6% and 4%, and reduces the standard deviation of delay up to 96%, 98%, 94%, 93%, 34%, 22%, 4%, 13%, 11%, 6%, 9%, 14%, 4%, 4%, 10% and 7% for a given throughput level, respectively in relation to other release polices: FRCP, EWIP, TOTAL_CT, PWR, EWC, DRCP, CONLOAD, WIPLCtrl, Droll, DEC, CONWIP, SA, RCONWIP, WR, CONSTBWL and CONSTWL respectively in integration with dispatching rule: SRPT. These improvements can also be understood from another aspect, that is, LWC can increase the system throughput rate for a given cycle time. The improvement is statistically significant according to the two sample t-test for all throughput values with a 95% confidence level. As the improvement of the proposed release policy: LWC is relatively less on the proposed release policies: CONSTWL and CONSTBWL with respect to mean delay, it can be inferred that the performance of CONSTWL and CONSTBWL is relatively better than other existing closed loop release policies for the scenarios considered in the simulation model. However, the best release policy: LWC provides satisfactory performance in comparison with other release policies for almost all scenarios considered in the simulation model. It is important to note that these proposed release policies can be easily applied in real wafer manufacturing systems because it possesses a simple logic and only the reference level need to be prescribed. The performance of four existing closed release policies that are FRCP, EWIP, TOTAL_CT and PWR are relatively worst in comparison with open loop release policy CONST. This is contradicting to the conclusions given in the literature by many authors that closed loop release policies are always better than open loop release policy with respect to cycle time and throughput measures. In fact, a reasonable closed loop release policy can provide better results than open loop release policy, if its objective and the release parameter are designed carefully, so that the release parameter can respond effectively to the dynamics of the manufacturing system. The reason for worst performance of these four existing closed loop release policies in comparison with open loop release policy and other existing policies is described in detail in this study. In order to see the impact of dispatching rules on a particular work station, batch machine work station, which usually has highest processing time in fabrication process, is considered in this study. The entire simulation experiments are replicated in the same manner except the basis that dispatching rules are applied on batch machine work station instead of bottleneck work station. Based on the analysis of the simulation results, the important observations are as follow: It is observed from the overall inferences that the influence of dispatching rules when applied to batch processing machine (diffusion) work station was not much on individual release policies, since the performance of all three dispatching rules provides nearly same performance at higher throughput level in the proposed simulation model. However, the performances of dispatching rule: SRPT in integration with all release policies considered in this study are summarized here because it produces less mean delay at most of the throughput values. In addition, from the analysis of simulation model, the proposed release policy: LWC reduces the average delay up to 97%, 93%, 87%, 85%, 22%, 17%, 15%, 15%, 13%, 11%, 10%, 10%, 9%, 6%, 6% and 2%, and reduces the standard deviation of delay up to 96%, 97%, 92%, 93%, 21%, 5%, 10%, 2%, 16%, 7%, 14%, 4%, 20%, 10%, 10% and 11% for a given throughput level, respectively in relation to FRCP, EWIP, PWR, TOTAL_CT, EWC, DEC, Droll, CONLOAD, SA, RCONWIP, WIPLCtrl, WR, DRCP, CONWIP, CONSTWL and CONSTBWL in integration with dispatching rule: SRPT, when applied on batch processing machine work station. The improvement is statistically significant according to the two sample t-test for most of the throughput values with a 95% confidence level. It is observed from overall inferences that the performance of all the release policies, considered in this study, in integration with dispatching rule: SRPT is better with respect to both mean delay and standard deviation of delay, when the dispatching rule is applied on the bottleneck (discrete machine, lithography) work station in the proposed simulation model. The performance of most of the release policies, considered in this study, in integration with dispatching rule: LIFO is better with respect to standard deviation of delay, when the dispatching rule is applied on the batch (batch machine, diffusion) work station. These results indicate that there is an influence of dispatching rule on the performance of wafer fabrication system if applied on batch machine work station or on bottleneck work station in integration with release policies. In addition, the effects of dispatching rules are highly dependent upon both the type of release policy used and the work station on which it is applied. Overall, the performance of the proposed release policies is proven to be very effective to system variability’s in scenarios considered in the simulation model. The significant impact of the choice of release policies on wafer manufacturing system performance is justified by the simulation experiments. It can be safely concluded that the efficient closed loop release policies that utilizes system information carefully based on the global factory state data can significantly improve the performance of wafer fabrication system. This thesis provides an extensive literature review covering several aspects of wafer fabrication process. Thereafter, a three new efficient closed loop release policies are developed and their workability are conceptually demonstrated with a framework and a flow diagram. The strength and the weakness of the existing release policies are conceptually highlighted and later it is proven to be true through comprehensive simulation study. A simulation model is developed by considering all the real-life fabrication environment for evaluating the performance of release policies in integration with dispatching rules. Cause and effect analysis is explored in proposed simulation model to set the parameters value. A series of simulation experiments are also constructed to empirically justify the conceptual significance of the proposed release policies.