A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital converter. Using nonregular feedback capacitors achieves better linearity than using conventional regular feedback capacitors in the multiplying digital-to-analog converter. The accuracy of this pipelined analog-to-digital converter can be also improved, the result shows that the DNL is ¡Ó0.31 LSB, INL is about ¡Ó0.57LSB.
Our proposed pipelined analog-to-digital converter is designed by TSMC 2P4M 0.35um process. It operates at 3.3V power supply voltage with 0.5 to 2.5V reference voltage, and the power consumption is about 64mW.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0714104-174845 |
| Date | 14 July 2004 |
| Creators | Wang, Chun-Ta |
| Contributors | Shyh-Jye Jou, Yao-Tsung Tsai, Jyi-Tsong Lin, Chia-Hsiung Kao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714104-174845 |
| Rights | not_available, Copyright information available at source archive |
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