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Improving processor efficiency by exploiting common-case behaviors of memory instructions

Processor efficiency can be described with the help of a number of  desirable
effects or metrics, for example, performance, power, area, design
complexity and access latency.
These metrics serve as valuable tools used in designing new processors
and they also act as  effective standards for comparing current processors.
Various factors impact the efficiency of modern out-of-order processors
and one important factor is the manner in which instructions are processed
through the processor pipeline.
In this dissertation research, we study the impact of load and store
instructions
(collectively known as memory instructions) on processor efficiency,
 and show how to improve efficiency by exploiting common-case or
 predictable patterns in the behavior of memory instructions.

The memory behavior patterns that we focus on in our research are
the predictability of memory dependences, the predictability in
data forwarding patterns,
  predictability in instruction criticality and conservativeness
in resource allocation and
deallocation policies.
We first design a scalable  and high-performance memory dependence
predictor and then apply
accurate memory dependence prediction to improve the efficiency of
the fetch engine of a simultaneous multi-threaded processor.
We then use predictable data forwarding patterns to eliminate power-hungry
 hardware in the processor with no loss in performance.  We then move to
 studying instruction criticality to improve
 processor efficiency. We study the behavior of critical load instructions
 and propose applications that can be optimized using  predictable,
load-criticality
 information. Finally, we explore conventional techniques for
allocation and deallocation
 of critical structures that process memory instructions and propose new
techniques to optimize the same.  Our new designs have the potential to reduce
 the power and the area required by processors significantly without losing
 performance, which lead to efficient designs of processors.

Identiferoai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/28165
Date02 January 2009
CreatorsSubramaniam, Samantika
PublisherGeorgia Institute of Technology
Source SetsGeorgia Tech Electronic Thesis and Dissertation Archive
Detected LanguageEnglish
TypeDissertation

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