The SRAM memory generator in this thesis is divided into four parts: row decoder, storage cell, column decoder, and sense amplifier & write controller. The row decoder is designed using pass-transistors logic with better area and regularity compared with conventional NAND based decoders. Two different column decoders, tree structure and NOR based predecoder, are provided in current version. Although only SRAM is implemented in this thesis, the memory generator platform is complete with all the necessary models required in the embedded design. In the future, other memories, such as cache, shift register, FIFO, stacks, ROM, register files, and content addressable memory, can be integrated in this memory generator platform.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0818104-191756 |
| Date | 18 August 2004 |
| Creators | Lee, Wan-Ping |
| Contributors | Shen-Fu Hsiao, Chien-Hsing Wu, Wei-Chih Hsu, Chua-Chin Wang, Ko-Chi Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818104-191756 |
| Rights | unrestricted, Copyright information available at source archive |
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