Network topologies play a vital role in chip design; they largely determine the cost of the network and significantly impact performance in many-core architectures. We propose a novel set of on-chip networks, dodecs, and illustrate how they reduce network diameter with randomized low-radix router connections. In addition, we design an adaptive routing algorithm for dodec networks to achieve high throughput. By introducing randomness, dodec networks exhibit more uniform message latency. By using low-radix routers, dodec networks simplify the router microarchitecture and attain 20% area and 22% power reduction compared to mesh routers while delivering the same overall application performance for PARSEC. We compare our dodec network to alternative low-radix network topologies and show that at the same cost, dodec networks increase the throughput up to 50% while reducing average latency by 10% compared to a mesh.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/43350 |
| Date | 11 December 2013 |
| Creators | Yang, Haofan |
| Contributors | Enright Jerger, Natalie |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.0024 seconds