The ubiquity of Internet connectivity means there is a greater need for computer network safety and security. Cost-effective secure computing networks and broadband applications not only need a sophisticated cryptosystem to accelerate data encryption, but also need substantial computational power to handle large data streams. Reconfigurable System-on-Chip (rSoC) technology is well suited to accelerate network cryptographic applications by implementing the entire computing application on a single reconfigurable chip. Hardware-software co-design and hardware-software communication are some key questions involved in using this rSoC technology. This thesis investigates how best to accelerate a cryptographic application using rSoC technology. Some background on FPGAs, reconfigurable computing, inter-process communication methods, hardware/software co-design, cryptography in general, and 3DES in particular are firstly introduced. Some existing reconfigurable computing systems and 3DES implementations on FPGA are then reviewed and analyzed. A new general hardware-software architecture, which consists of a CPU, memories, customized peripherals and buses on a single FPGA chip, is designed to accelerate the security application. The 3DES application is divided into four functional modules: input, subkey generation, data processing, and output modules. Shared memory with semaphores is chosen for the inter-module communication. A complete inter-module communication solution is presented for hardware and software module communications. A generic component, HWCOM, is designed for those communications which involve hardware modules. Experimental results show that using two buffers as shared memories between communication modules and increasing shared memory size are good methods for transferring data between hardware/software modules more efficiently. When investigating the best hardware/software partition scheme, all 3DES modules are first executed in software on the FPGA. The experimental results of 83Kbps encryption throughput indicate that the software-only solution is not satisfactory. Through profiling, the bottleneck is shown to be the data processing module and the subkey generation module, which are then implemented in hardware. Experimental results show an improved 179Mbps throughput. This presents over 2000 times acceleration compared to software and shows that the hardware-software co-implementation can efficiently accelerate the 3DES application with good performance and flexibility.
| Identifer | oai:union.ndltd.org:ADTP/252969 |
| Creators | Chen, Yi |
| Source Sets | Australiasian Digital Theses Program |
| Detected Language | English |
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