In this paper, we propose an area-time efficient design for redundant CORDIC-based SIN/COS evaluation by predict on the polarity of micro-rotations using a novel technique called ¡§Base Transfer angle Decomposition Algorithm¡¨(BTDA). The proposed design benefits from a constant scaling and requires no correcting iterations. By predicting the polarity of the signed bit of the micro-rotation, the critical paths of the unfolded and the pipelined designs involve only the X and Y recurrences. The implementations of BTDA architectures for 24-bit wide CORDIC-Base SIN/COS generator were synthesized using FPGA tools (XILINX Foundation Series version 2.1i), and the area-time complexities are presented for unfolded as well as pipelined designs. The proposed design results save more than 25% hardware area with speed-up of more than 30% compared with the exiting methods.
Keywords: CORDIC, BTDA, Redundant, SIN/COS, FPGA
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0803100-153348 |
| Date | 03 August 2000 |
| Creators | Chao-Chuan, Huang |
| Contributors | Shen-Fu Hsiao. |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803100-153348 |
| Rights | off_campus_withheld, Copyright information available at source archive |
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