<p>This master thesis describes the creation of a fully parameterizable design tool, intended for automatic generation of standard cell layouts from basic schematic information. The thesis covers general background on programs for automatic layout generation, standard cells and basics in IC design. Algorithms commonly used in various parts of such programs are presented, and the ones used to implement the tool are described in depth.</p>
| Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-1712 |
| Date | January 2003 |
| Creators | Ekebrand, Terese, Funke, Nils |
| Publisher | Linköping University, Department of Electrical Engineering, Linköping University, Department of Electrical Engineering, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, text |
| Relation | LiTH-ISY-Ex, ; 3303 |
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