The ever-increasing complexity and size of current circuit designs have made testing and verification major bottlenecks in the design flow of VLSI (Very Large Scale Integrated) circuits. Statistics show that more than 70% of the design effort can be spent on functional verification and manufacturing testing. This percentage is expected to increase in the future if no significant strides in these areas are made. In this dissertation, we target three related problems in simulation-based Design Verification and Testing: Sequential ATPG (Automatic Test Pattern Generation), Unbounded Model Checking (UMC) of safety properties, and low power testing for full-scan sequential circuits. We model these three problems as simulation-based pattern generation problems and exploit novel ATPG algorithms to increase the effectiveness of sequential ATPGs.
The main challenge for fault/error detection in sequential circuits is the large number of flip-flops (FFs) in modern designs. Due to the large number and variable length of test sequences required for such circuits, the existing deterministic ATPG algorithms fail to achieve high test coverages. Such algorithms typically work by first unrolling the sequential circuit and then performing frequent backtracking to generate test vectors for fault detection. For the hard-to-detect faults, these schemes either run out of memory or require a huge computational effort. We show that simulation-based ATPGs, on the other hand, scale very well for large circuits as they perform only forward simulation. A fundamental problem associated with simulation-based ATPGs is to avoid exhaustive circuit simulation, which is impractical for large designs in the real world, by choosing high quality test vectors that achieve a high test coverage within a low simulation time. We tackle this primary problem by exploiting different correlation-based heuristics.
The intuition behind using correlation-based heuristics is to better guide the pattern generation engine such that the specific objective of either fault detection or property verification in UMC or minimizing power consumption during the testing, is achieved in an efficient manner without resorting to exhaustive simulation. In particular, we model and explore the following correlations: (1) temporal correlations, i.e. correlations on each primary input (PI) in different time frames, and (2) spatial correlations, i.e. correlations among different FFs in the same time frame. We employ temporal correlations in the context of pattern generation of a built-in-self-test (BIST) architecture and we explore spatial correlations to guide a logic-simulation-based sequential ATPG and low power scan test generation. Experimental results on ISCAS and ITC benchmark circuits have shown that those correlations can enhance the simulation to discover more faults or design errors in a significantly shorter time. / Ph. D.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/28342 |
| Date | 19 September 2006 |
| Creators | Chen, Xiaoding |
| Contributors | Electrical and Computer Engineering, Hsiao, Michael S., Shukla, Sandeep K., Martin, Thomas L., Lu, Guo-Quan, Edwards, Stephen H. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Dissertation |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | xiaoding_dissertation.pdf |
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