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Electrical Analysis of 65nm MOSFETs under Process and Mechanical Stress

In recent years, in order to promote the MOSFET¡¦s frequency and performance, the dimension keeping scale down, we can get more transistors in the same area. But nowadays the development of the lithography technology has come to the bottleneck, we must find the other way to improve the performance of transistor. In this study, the strained silicon effect and reliability of CMOS are fully discussed.
In order to get strain from the channel, by process, deposit Si3N4 at NMOS and adopt the silicon-germanium epitaxy on source/drain by PMOS, can effective improve NMOS and PMOS electronic characteristic. Besides, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress by NMOS and strain due to uniaxial compressive stress by PMOS. By these ways, we successfully improve drain current and mobility of NMOS and PMOS.
Furthermore, this study is also probing into strain silicon at low temperature, the impacts on electronic characteristic by different scattering mechanism.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0730107-003801
Date30 July 2007
CreatorsChen, Chun-nan
ContributorsHerng-Yih Ueng, Yeu-Long Jiang, Ting-Chang Chang, Yu-Feng Huang, Wei-Chou Hsu
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730107-003801
Rightsnot_available, Copyright information available at source archive

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