The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator.
The proposed Sigma Delta modulator uses TSMC 0.18£gm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0901110-122544 |
| Date | 01 September 2010 |
| Creators | Chen, Chih-hung |
| Contributors | Ko-chi Kuo, Chia-hsiung Kao, Tzu-sheng Hung |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544 |
| Rights | campus_withheld, Copyright information available at source archive |
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