In this thesis, we introduce a methodology to design and implement a Homeplug1.0 channel decoder that is completely conforming to Homeplug 1.0 specifications definedin HomePlug Power-line Alliance Standard (HPA) including Reed-solomon decoding,Viterbi decoding, punctured ,and de-interleaving technologies. Further, by using
MATLAB/Simullink software, Xilinx System Generator, Xilinx Alliance tools, XilinxISE and Modelsim SE software, we build up a transceiver platform to simulate and analyze the performance of the power-line channel decoder based on FPGA hardware
implementation. The hardware can be used directly in practical Homeplug 1.0 systems.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0901110-183033 |
| Date | 01 September 2010 |
| Creators | Liu, Jia-Young |
| Contributors | Pei-Yin Chen, Tsang-Yi Wang, Chao-Tang Yu |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-183033 |
| Rights | campus_withheld, Copyright information available at source archive |
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