This thesis investigates Electronic System Level (ESL) design flow by implementing some applications using CoWare ESL tool, ConvergenSC. There are three focuses in this thesis: basic cell modeling, system platform design, and system level architecture exploration. In the basic cell modeling, we adopt the system level language, SystemC, to describe the abstract behavior of various modules in Transaction Level Modeling (TLM). In system platform design, we use the ESL tool to create system platforms of different architectures, mainly AMBA-based system platforms. In the system architecture exploration, we analyze the simulation results in different system platform architectures and present several strategies (memory allocation, ASIC design, DMA, Pipeline Scheduling) to improve the overall system performance in the application example of MP3 decoder. The rough estimation of power and area is also included in the system architecture exploration stage.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0815106-105748 |
| Date | 15 August 2006 |
| Creators | Chang, Yao-Jui |
| Contributors | Shiann-Rong Kuang, Shen-Fu Hsiao, Jih-Ching Chiu, Chung-Ho Chen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815106-105748 |
| Rights | campus_withheld, Copyright information available at source archive |
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