This thesis investigates Electronic System Level (ESL) design flow by implementing some applications using CoWare ESL tool, ConvergenSC. There are three focuses in this thesis: basic cell modeling, system platform design, and system level architecture exploration. In the basic cell modeling, we adopt the system level language, SystemC, to describe the abstract behavior of various modules in Transaction Level Modeling (TLM). In system platform design, we use the ESL tool to create system platforms of different architectures, mainly AMBA-based system platforms. In the system architecture exploration, we analyze the simulation results in different system platform architectures and present several strategies (memory allocation, ASIC design, DMA, Pipeline Scheduling) to improve the overall system performance in the application example of MP3 decoder. The rough estimation of power and area is also included in the system architecture exploration stage.

With complexities of Systems-on-Chip rising almost daily, the system designers have been searching for new methodology that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However, the most important things that system designers care about are system architectures (components topology), HW/SW performance, and the communication protocols. System designer has to make decisions on these factors in a very short time. Furthermore, the transaction level model (TLM) can satisfy the requests on simulation speed and the information that system designer need. We implement a TLM virtual prototype platform with SystemC composing with the variable wrappers. The basic modules: ISS interface, user-define modules and a flexible bus. Based on the infrastructures, a much faster modeling process of the system can be achieved in this thesis. Finally, the platform will run the whole-system-simulation to verify the functional model and collect the dynamic information on the buses and IPs to diagnose the bottle-neck of the system.

Development of embedded systems poses an increasing challenge fordevelopers largely due to increasing complexity. Several factors contribute tothe complexity challenge: • the number of extra-functional properties applying to embedded systems,such as resource usage, timing effects, safety. • the functionality of embedded systems, to a larger extent than for othersoftware, involves engineers from multiple different disciplines, such asmechanical, control, software, safety, systems and electrical engineers.Themulti-disciplinarity causes the development environments to consistof separate data, models and tools. Several engineering paradigms to handle this complexity increase havebeen suggested, including methodologies focused on architecture, models andcomponents. In systems engineering, a long-standing approach has been todescribe the system in several views, each according to a certain viewpoint.By doing so, a divide-and-conquer strategy is applied to system concerns.Unfortunately, it is hard to always find completely independent concerns:there is always some semantic overlap between the different views. Modelbaseddesign (MBD) deals with building sound abstractions that can representa system under design and be used for analysis. Component-based design(CBD) focuses on how to build reusable component models with well-definedcomposition models. In this thesis, a concept of formalized multi-viewed component models (MVCM) is proposed, which integrates the three above mentioned paradigms.Principles and guidelines for MV CMs are developed. One of the main challengesfor the proposition is to provide MV CMs that produce composabilityboth along component boundaries and viewpoint boundaries. To accomplishthis, the relations between viewpoints need to be explicitly taken into account.Further, the semantic relations between these viewpoints need to be explicitlymodeled in order to efficiently ensure that the views are kept consistent. Asa main contribution, this thesis presents the formalization of the conceptsneeded to build such component models. A proper formalization of multiviewedconcerns provides several opportunities. Given suitable tool support, itwill be feasible to automate architecture analysis and architecture exploration. The thesis includes a number of case studies that provide insight andfeedback to the problem formulation and validating the results. The casestudies include a resource-aware reconfigurable middleware, a design of anarchitecture exploration methodology, and a windshield wiper system. / <p>QC 20130527</p>

Field-programmable analog arrays (FPAA) are integrated circuits with a collection of analog building blocks connected through a wire and switch fabric to achieve reconfigurability similar to the FPGAs of the digital domain. Like FPGAs, FPAAs can help reduce the time and money costs of the integrated circuit design cycle and make analog design much easier. In recent years, several types of FPAAs have been developed. Among these, FPAAs that use floating-gate transistors as programming elements have shown great potential in scalability because of the simplicity they provide in configuring the chip. Existing tools for programming FPAAs tend to be device specific and aimed at specific tasks such as filter design. To move FPAAs to the next step, more powerful and generic placement and routing tools are necessary. This thesis presents a placement and routing tool for large-scale floating-gate-based FPAAs. A topology independent routing resource graph (RRG) was used to model the FPAA routing topology, which enables generic description of any FPAA architecture with arbitrary connectivity including possible FPGA support in the future as well. So far, different FPAA architectures have been specified and routed successfully. The tool is already in use in classes and workshops for analog circuit and system design. Efficient ways to describe circuits and user constraints were developed to allow easy integration with other tools. Analog circuit performance was optimized by taking into account the routing parasitic effects on interconnects under various device-related constraints. Parasitic modeling allows simulation and evaluation of circuits routed on FPAA. Finally, a methodology was developed to explore the optimum architecture for a set of circuit classes by evaluating the efficiency of different architectures for each circuit class.