With complexities of Systems-on-Chip rising almost daily, the system designers have been searching for new methodology that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However, the most important things that system designers care about are system architectures (components topology), HW/SW performance, and the communication protocols. System designer has to make decisions on these factors in a very short time. Furthermore, the transaction level model (TLM) can satisfy the requests on simulation speed and the information that system designer need. We implement a TLM virtual prototype platform with SystemC composing with the variable wrappers. The basic modules: ISS interface, user-define modules and a flexible bus. Based on the infrastructures, a much faster modeling process of the system can be achieved in this thesis. Finally, the platform will run the whole-system-simulation to verify the functional model and collect the dynamic information on the buses and IPs to diagnose the bottle-neck of the system.