IEEE P1687 (IJTAG) is proposed to add more exibility|compared with IEEE 1149.1 JTAG|for accessing on-chip embedded test features called instruments. This exibility makes it possible to include and exclude instruments from the scan path. To reach a minimal test time, all instruments should be accessed concurrently. However, constraints such as power and resource constraints might limit concurrency. There is a need to consider power and resource constraints while developing the test schedule. This thesis consists of two parts. In the rst part, three test time calculation approaches, namely session-based test schedule with a xed scan path, session-based test schedule with a recongurable scan path, and session-less test schedule with a recongurable scan path are proposed. In the second part, three test scheduling approaches, namely session-based test scheduling, optimized session-based test scheduling, and optimized session-less test scheduling are studied and three algorithms are presented for each of the test scheduling approaches. Experiments are carried out using the test scheduling approaches and the results show that optimized sessionless test scheduling can signicantly reduce the test time compared with session-based test scheduling.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-81472 |
| Date | January 2012 |
| Creators | Asani, Golnaz |
| Publisher | Linköpings universitet, Institutionen för datavetenskap, Linköpings universitet, Tekniska högskolan |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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