by Hui Chau Man. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1991. / Includes bibliographical references. / ABSTRACT --- p.i / ACKNOWLEDGEMENTS --- p.ii / TABLE OF CONTENTS --- p.iii / Chapter CHAPTER 1 --- INTRODUCTION / Chapter 1.1 --- Computer Graphics Today --- p.2 / Chapter 1.1.1 --- 3D Graphics Synthesis Techniques --- p.2 / Chapter 1.1.2 --- Hardware-assisted Computer Graphics --- p.4 / Chapter 1.2 --- About The Thesis --- p.5 / Chapter CHAPTER 2 --- GRAPHICS SYSTEM ARCHITECTURES / Chapter 2.1 --- Basic Structure of a Graphics Subsystem --- p.8 / Chapter 2.2 --- VLSI Graphics Chips --- p.9 / Chapter 2.2.1 --- The CRT Controllers --- p.10 / Chapter 2.2.2 --- The VLSI Graphics Processors --- p.11 / Chapter 2.2.3 --- Design Philosophies for VLSI Graphics Processors --- p.12 / Chapter 2.3 --- Graphics Boards --- p.14 / Chapter 2.3.1 --- The ARTIST 10 Graphics Controller --- p.14 / Chapter 2.3.2 --- The MATROX PG-1281 Graphics Controller --- p.16 / Chapter 2.4 --- High-end Graphics System Architectures --- p.17 / Chapter 2.4.1 --- Graphics Accelerator with Multiple Functional Units --- p.18 / Chapter 2.4.2 --- Parallel Processing Graphics Systems --- p.18 / Chapter 2.4.3 --- The Parallel Processor Architecture --- p.19 / Chapter 2.4.4 --- The Pipelined Architecture --- p.21 / Chapter 2.5 --- Comparisons and Discussions --- p.22 / Chapter 2.5.1 --- Parallel Processors versus Pipelined Processing --- p.23 / Chapter 2.5.2 --- Parallel Processors versus Multiple Functional Units --- p.23 / Chapter 2.6 --- Summary of High-end Graphics Systems --- p.24 / Chapter CHAPTER 3 --- AN ISA 3D GRAPHICS DISPLAY SERVER / Chapter 3.1 --- Common ISA Graphics Cards --- p.26 / Chapter 3.1.1 --- Standard Video Display Cards --- p.26 / Chapter 3.1.2 --- Graphics Processing Boards --- p.27 / Chapter 3.2 --- A Depth Processor for the ISA computers --- p.28 / Chapter 3.2.1 --- The Z-buffer Algorithm for HLHSR --- p.28 / Chapter 3.2.2 --- Our Hardware Solution for HLHSR --- p.29 / Chapter 3.2.3 --- Design of the Depth Processor --- p.31 / Chapter 3.2.4 --- Structure of the Depth Processor --- p.34 / Chapter 3.2.5 --- The Depth Processor Operations --- p.35 / Chapter 3.2.6 --- Software Support --- p.40 / Chapter 3.2.7 --- Performance of the Depth Processor --- p.44 / Chapter 3.3 --- A VGA Accelerator for the ISA Computers --- p.45 / Chapter 3.3.1 --- Display Buffer Structure of the SuperVGA --- p.46 / Chapter 3.3.2 --- Design of the VGA Accelerator --- p.47 / Chapter 3.3.3 --- Structure of the VGA Accelerator --- p.49 / Chapter 3.3.4 --- Combining the VGA Accelerator and the Depth Processor --- p.51 / Chapter 3.3.5 --- Actual Performance of the DP-VA Board --- p.54 / Chapter 3.3.6 --- 3D Graphics Applications Using the DP-VA Board --- p.55 / Chapter 3.4 --- A 3D Graphics Display Server --- p.57 / Chapter 3.5 --- Host Connection for the 3D Graphics Display Server --- p.59 / Chapter 3.5.1 --- The Single Board Computers --- p.60 / Chapter 3.5.2 --- The VME-to-ISA bus convenor --- p.61 / Chapter 3.5.3 --- Structure of the VME-to-ISA Bus Convertor --- p.61 / Chapter 3.5.4 --- Communications through the bus convertor --- p.64 / Chapter 3.6 --- Physical Construction of the DP-VA Board and the Bus Convertor --- p.65 / Chapter 3.7 --- Summary --- p.66 / Chapter CHAPTER 4 --- A MULTI-i860 3D GRAPHICS SYSTEM / Chapter 4.1 --- The i860 Processor --- p.69 / Chapter 4.2 --- Design of a Multiprocessor 3D Graphics System --- p.70 / Chapter 4.2.1 --- A Reconfigurable Processor-Pipeline System --- p.72 / Chapter 4.2.2 --- The Depth-Processing Unit --- p.73 / Chapter 4.2.3 --- A Multiprocessor Graphics System --- p.75 / Chapter 4.3 --- Structure of the Multi-i860 3D --- p.77 / Chapter 4.3.1 --- The 64-bit-wide Global Data Buses --- p.77 / Chapter 4.3.2 --- The 1280x1024 True-colour Display Unit --- p.79 / Chapter 4.3.3 --- The Depth Processing Unit --- p.82 / Chapter 4.3.4 --- The i860 Processing Units --- p.84 / Chapter 4.3.5 --- The System Control Unit --- p.87 / Chapter 4.3.6 --- Performance Prediction --- p.89 / Chapter 4.4 --- Summary --- p.90 / Chapter CHAPTER 5 --- CONCLUSIONS / Chapter 5.1 --- The 3D Graphics Synthesis Pipeline ……… --- p.91 / Chapter 5.2 --- 3D Graphics Hardware --- p.91 / Chapter 5.3 --- Design Approach for the ISA 3D Graphics Display Server --- p.92 / Chapter 5.4 --- Flexibility in the Multi-i860 3D Graphics System --- p.93 / Chapter 5.5 --- Future Work --- p.94 / Chapter APPENDIX A --- DISPLAYING REALISTIC 3D SCENES / Chapter A.1 --- Modelling 3D Objects in Boundary Representation --- p.96 / Chapter A.2 --- Transformations of 3D scenes --- p.98 / Chapter A.2.1 --- Composite Modelling Transformation --- p.98 / Chapter A.2.2 --- Viewing Transformations --- p.99 / Chapter A.2.3 --- Projection --- p.102 / Chapter A.2.4 --- Window to Viewport Mapping --- p.104 / Chapter A.3 --- Implementation of the Viewing Pipeline --- p.105 / Chapter A.3.1 --- Defining the View Volume --- p.105 / Chapter A.3.2 --- Normalization of The View Volume --- p.106 / Chapter A.3.3 --- The Overall Transformation Pipeline --- p.108 / Chapter A.4 --- Rendering Realistic 3D Scenes --- p.108 / Chapter A.4.1 --- Scan-conversion of Lines and Polygons --- p.108 / Chapter A.4.2 --- Hidden Surface Removal --- p.109 / Chapter A.4.3 --- Shading --- p.112 / Chapter A.4.4 --- The Complete 3D Graphics Pipeline --- p.114 / Chapter APPENDIX B --- DEPTH PROCESSOR DESIGN DETAILS / Chapter B.l --- PAL Definitions --- p.116 / Chapter B.2 --- Circuit Diagrams --- p.118 / Chapter B.3 --- Depth Processor User's Guide --- p.121 / Chapter APPENDIX C --- VGA ACCELERATOR DESIGN DETAILS / Chapter C.1 --- PAL Definitions --- p.124 / Chapter C.2 --- Circuit Diagram --- p.125 / Chapter C.3 --- The DP-VA User's Guide --- p.127 / Chapter APPENDIX D --- VME-TO-ISA BUS CONVERTOR DESIGN DETAILS / Chapter D.1 --- PAL Definitions --- p.131 / Chapter D.2 --- Circuit Diagrams --- p.133 / Chapter APPENDIX E --- 3D GRAPHICS LIBRARY ROUTINES FOR THE DP-VA BOARD / Chapter E.1 --- 3D Drawing Routines --- p.136 / Chapter E.2 --- 3D Transformation Routines --- p.137 / Chapter E.3 --- Shading Routines --- p.138 / Chapter APPENDIX F --- PIPELINE CONFIGURATIONS FOR N PROCESSORS / REFERENCES
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_318751 |
| Date | January 1991 |
| Contributors | Hui, Chau Man., Chinese University of Hong Kong Graduate School. Division of Computer Science. |
| Publisher | Chinese University of Hong Kong |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, vi, 143 p. : ill. (some col.) ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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