Return to search

Verifying IP-Cores by Mapping Gate to RTL-Level Designs

No description available.
Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:case1385975878
Date January 2013
CreatorsJangid, Anuradha
PublisherCase Western Reserve University School of Graduate Studies / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=case1385975878
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

Page generated in 0.0021 seconds